From mboxrd@z Thu Jan 1 00:00:00 1970 From: w@1wt.eu (Willy Tarreau) Date: Wed, 18 Sep 2013 18:49:48 +0200 Subject: mvneta: oops in __rcu_read_lock on mirabox In-Reply-To: <20130918183549.3e7b8f4c@skate> References: <20130916163937.GC3188@1wt.eu> <20130916164412.GD3188@1wt.eu> <20130916174708.GG3188@1wt.eu> <20130916182807.GO12758@n2100.arm.linux.org.uk> <20130917060111.GB9325@1wt.eu> <20130918183549.3e7b8f4c@skate> Message-ID: <20130918164948.GA18754@1wt.eu> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Wed, Sep 18, 2013 at 06:35:49PM +0200, Thomas Petazzoni wrote: > Dear Ethan Tuttle, > > On Tue, 17 Sep 2013 23:30:56 -0700, Ethan Tuttle wrote: > > On Mon, Sep 16, 2013 at 11:01 PM, Willy Tarreau wrote: > > > Next step should be that you test both kernels to be sure. > > > > Thanks for the kernel images, Willy. I'm still experimenting but > > initial results are strange: I haven't seen a crash from the -ethan > > image you provided, nor by a kernel with that config that I built > > myself. The config is only different from my crashing config by a few > > options. So perhaps some combination of options prevents the crash. > > I'll see if I can narrow it down. > > A toolchain generating some crappy code maybe? Ethan, Willy, comparing > your toolchain (compiler version, origin of the toolchain) could be > interesting. I thought about this but it looks suspicious, I don't see why the toolchain would produce random bitflips. My toolchain is a linaro 4.7 gcc into which I have added support for a "pj4b" CPU target which is essentially the same as cortex-a9 plus support for the IDIV instruction in thumb mode. But I can send it to Ethan if that helps. Willy From mboxrd@z Thu Jan 1 00:00:00 1970 From: Willy Tarreau Subject: Re: mvneta: oops in __rcu_read_lock on mirabox Date: Wed, 18 Sep 2013 18:49:48 +0200 Message-ID: <20130918164948.GA18754@1wt.eu> References: <20130916163937.GC3188@1wt.eu> <20130916164412.GD3188@1wt.eu> <20130916174708.GG3188@1wt.eu> <20130916182807.GO12758@n2100.arm.linux.org.uk> <20130917060111.GB9325@1wt.eu> <20130918183549.3e7b8f4c@skate> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: Ethan Tuttle , Russell King - ARM Linux , Andrew Lunn , Jason Cooper , netdev@vger.kernel.org, Ezequiel Garcia , Gregory =?iso-8859-1?Q?Cl=E9ment?= , linux-arm-kernel@lists.infradead.org To: Thomas Petazzoni Return-path: Received: from 1wt.eu ([62.212.114.60]:40066 "EHLO 1wt.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752055Ab3IRQuX (ORCPT ); Wed, 18 Sep 2013 12:50:23 -0400 Content-Disposition: inline In-Reply-To: <20130918183549.3e7b8f4c@skate> Sender: netdev-owner@vger.kernel.org List-ID: On Wed, Sep 18, 2013 at 06:35:49PM +0200, Thomas Petazzoni wrote: > Dear Ethan Tuttle, > > On Tue, 17 Sep 2013 23:30:56 -0700, Ethan Tuttle wrote: > > On Mon, Sep 16, 2013 at 11:01 PM, Willy Tarreau wrote: > > > Next step should be that you test both kernels to be sure. > > > > Thanks for the kernel images, Willy. I'm still experimenting but > > initial results are strange: I haven't seen a crash from the -ethan > > image you provided, nor by a kernel with that config that I built > > myself. The config is only different from my crashing config by a few > > options. So perhaps some combination of options prevents the crash. > > I'll see if I can narrow it down. > > A toolchain generating some crappy code maybe? Ethan, Willy, comparing > your toolchain (compiler version, origin of the toolchain) could be > interesting. I thought about this but it looks suspicious, I don't see why the toolchain would produce random bitflips. My toolchain is a linaro 4.7 gcc into which I have added support for a "pj4b" CPU target which is essentially the same as cortex-a9 plus support for the IDIV instruction in thumb mode. But I can send it to Ethan if that helps. Willy