diff for duplicates of <20130927160406.GY9093@linux.vnet.ibm.com> diff --git a/a/1.txt b/N1/1.txt index e724dc8..94f6aaf 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -11,7 +11,7 @@ On Fri, Sep 27, 2013 at 05:34:34PM +0200, Peter Zijlstra wrote: > > CPU 2: r1 = ACCESS_ONCE(x); r2 = ACCESS_ONCE(x); > > > > Itanium architects have told me that it really is possible for CPU 2 to -> > see r1=1 and r2=0. Placing a memory barrier between CPU 2's pair of +> > see r1==1 and r2==0. Placing a memory barrier between CPU 2's pair of > > fetches prevents this, but without any other memory barrier to pair with. > > Oh man.. its really past time to sink that itanic already. @@ -33,3 +33,9 @@ that the probability of misordering is quite low. But again, the ball is firmly in the Itanium maintainers' courts, and I have added them on CC. Thanx, Paul + +-- +To unsubscribe, send a message with 'unsubscribe linux-mm' in +the body to majordomo@kvack.org. For more info on Linux MM, +see: http://www.linux-mm.org/ . +Don't email: <a href=mailto:"dont@kvack.org"> email@kvack.org </a> diff --git a/a/content_digest b/N1/content_digest index a4ad767..34ae895 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -10,7 +10,7 @@ "ref\020130927153434.GG15690@laptop.programming.kicks-ass.net\0" "From\0Paul E. McKenney <paulmck@linux.vnet.ibm.com>\0" "Subject\0Re: [PATCH] checkpatch: Make the memory barrier test noisier\0" - "Date\0Fri, 27 Sep 2013 16:04:06 +0000\0" + "Date\0Fri, 27 Sep 2013 09:04:06 -0700\0" "To\0Peter Zijlstra <peterz@infradead.org>\0" "Cc\0Joe Perches <joe@perches.com>" Ingo Molnar <mingo@kernel.org> @@ -48,7 +48,7 @@ "> > CPU 2: r1 = ACCESS_ONCE(x); r2 = ACCESS_ONCE(x);\n" "> > \n" "> > Itanium architects have told me that it really is possible for CPU 2 to\n" - "> > see r1=1 and r2=0. Placing a memory barrier between CPU 2's pair of\n" + "> > see r1==1 and r2==0. Placing a memory barrier between CPU 2's pair of\n" "> > fetches prevents this, but without any other memory barrier to pair with.\n" "> \n" "> Oh man.. its really past time to sink that itanic already.\n" @@ -69,6 +69,12 @@ "that the probability of misordering is quite low. But again, the ball\n" "is firmly in the Itanium maintainers' courts, and I have added them on CC.\n" "\n" - "\t\t\t\t\t\t\tThanx, Paul" + "\t\t\t\t\t\t\tThanx, Paul\n" + "\n" + "--\n" + "To unsubscribe, send a message with 'unsubscribe linux-mm' in\n" + "the body to majordomo@kvack.org. For more info on Linux MM,\n" + "see: http://www.linux-mm.org/ .\n" + "Don't email: <a href=mailto:\"dont@kvack.org\"> email@kvack.org </a>" -110cd550dfe27a5afb6427121fc28d9f26cebac5e3c69c478a3d4d95d822e415 +ee3bc067db1f4b859f39f3a6d7d8af28e17571ffdd5e094efc7c85194c763d2b
diff --git a/a/1.txt b/N2/1.txt index e724dc8..b07b893 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -11,7 +11,7 @@ On Fri, Sep 27, 2013 at 05:34:34PM +0200, Peter Zijlstra wrote: > > CPU 2: r1 = ACCESS_ONCE(x); r2 = ACCESS_ONCE(x); > > > > Itanium architects have told me that it really is possible for CPU 2 to -> > see r1=1 and r2=0. Placing a memory barrier between CPU 2's pair of +> > see r1==1 and r2==0. Placing a memory barrier between CPU 2's pair of > > fetches prevents this, but without any other memory barrier to pair with. > > Oh man.. its really past time to sink that itanic already. diff --git a/a/content_digest b/N2/content_digest index a4ad767..e9879dc 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -10,7 +10,7 @@ "ref\020130927153434.GG15690@laptop.programming.kicks-ass.net\0" "From\0Paul E. McKenney <paulmck@linux.vnet.ibm.com>\0" "Subject\0Re: [PATCH] checkpatch: Make the memory barrier test noisier\0" - "Date\0Fri, 27 Sep 2013 16:04:06 +0000\0" + "Date\0Fri, 27 Sep 2013 09:04:06 -0700\0" "To\0Peter Zijlstra <peterz@infradead.org>\0" "Cc\0Joe Perches <joe@perches.com>" Ingo Molnar <mingo@kernel.org> @@ -48,7 +48,7 @@ "> > CPU 2: r1 = ACCESS_ONCE(x); r2 = ACCESS_ONCE(x);\n" "> > \n" "> > Itanium architects have told me that it really is possible for CPU 2 to\n" - "> > see r1=1 and r2=0. Placing a memory barrier between CPU 2's pair of\n" + "> > see r1==1 and r2==0. Placing a memory barrier between CPU 2's pair of\n" "> > fetches prevents this, but without any other memory barrier to pair with.\n" "> \n" "> Oh man.. its really past time to sink that itanic already.\n" @@ -71,4 +71,4 @@ "\n" "\t\t\t\t\t\t\tThanx, Paul" -110cd550dfe27a5afb6427121fc28d9f26cebac5e3c69c478a3d4d95d822e415 +ebcbfe7265ebc1b642a746d18f22c2b7b3d35cd435120f56a16b08795da665fd
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