From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/dp: constify DP DPCD helpers Date: Fri, 27 Sep 2013 19:11:49 +0300 Message-ID: <20130927161149.GI14385@intel.com> References: <1380297661-13474-1-git-send-email-jani.nikula@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 16415E5CEE for ; Fri, 27 Sep 2013 09:11:54 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1380297661-13474-1-git-send-email-jani.nikula@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org Errors-To: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org To: Jani Nikula Cc: dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org On Fri, Sep 27, 2013 at 07:01:01PM +0300, Jani Nikula wrote: > None of the DP DPCD helpers need to modify the DPCD. > = > Signed-off-by: Jani Nikula Reviewed-by: Ville Syrj=E4l=E4 > --- > drivers/gpu/drm/drm_dp_helper.c | 16 ++++++++-------- > include/drm/drm_dp_helper.h | 16 ++++++++-------- > 2 files changed, 16 insertions(+), 16 deletions(-) > = > diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_hel= per.c > index 89e1966..9e978aa 100644 > --- a/drivers/gpu/drm/drm_dp_helper.c > +++ b/drivers/gpu/drm/drm_dp_helper.c > @@ -228,12 +228,12 @@ i2c_dp_aux_add_bus(struct i2c_adapter *adapter) > EXPORT_SYMBOL(i2c_dp_aux_add_bus); > = > /* Helpers for DP link training */ > -static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r) > +static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int = r) > { > return link_status[r - DP_LANE0_1_STATUS]; > } > = > -static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE], > +static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE], > int lane) > { > int i =3D DP_LANE0_1_STATUS + (lane >> 1); > @@ -242,7 +242,7 @@ static u8 dp_get_lane_status(u8 link_status[DP_LINK_S= TATUS_SIZE], > return (l >> s) & 0xf; > } > = > -bool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE], > +bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], > int lane_count) > { > u8 lane_align; > @@ -262,7 +262,7 @@ bool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STAT= US_SIZE], > } > EXPORT_SYMBOL(drm_dp_channel_eq_ok); > = > -bool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE], > +bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], > int lane_count) > { > int lane; > @@ -277,7 +277,7 @@ bool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_= STATUS_SIZE], > } > EXPORT_SYMBOL(drm_dp_clock_recovery_ok); > = > -u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE], > +u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS= _SIZE], > int lane) > { > int i =3D DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); > @@ -290,7 +290,7 @@ u8 drm_dp_get_adjust_request_voltage(u8 link_status[D= P_LINK_STATUS_SIZE], > } > EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage); > = > -u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_= SIZE], > +u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_S= TATUS_SIZE], > int lane) > { > int i =3D DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); > @@ -303,7 +303,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_sta= tus[DP_LINK_STATUS_SIZE], > } > EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis); > = > -void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE= ]) { > +void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CA= P_SIZE]) { > if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] =3D=3D 0) > udelay(100); > else > @@ -311,7 +311,7 @@ void drm_dp_link_train_clock_recovery_delay(u8 dpcd[D= P_RECEIVER_CAP_SIZE]) { > } > EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay); > = > -void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]) { > +void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SI= ZE]) { > if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] =3D=3D 0) > udelay(400); > else > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > index ae8dbfb..88661ad 100644 > --- a/include/drm/drm_dp_helper.h > +++ b/include/drm/drm_dp_helper.h > @@ -333,20 +333,20 @@ i2c_dp_aux_add_bus(struct i2c_adapter *adapter); > = > = > #define DP_LINK_STATUS_SIZE 6 > -bool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE], > +bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], > int lane_count); > -bool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE], > +bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], > int lane_count); > -u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE], > +u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS= _SIZE], > int lane); > -u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_= SIZE], > +u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_S= TATUS_SIZE], > int lane); > = > #define DP_RECEIVER_CAP_SIZE 0xf > #define EDP_PSR_RECEIVER_CAP_SIZE 2 > = > -void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE= ]); > -void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]); > +void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CA= P_SIZE]); > +void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SI= ZE]); > = > u8 drm_dp_link_rate_to_bw_code(int link_rate); > int drm_dp_bw_code_to_link_rate(u8 link_bw); > @@ -379,13 +379,13 @@ struct edp_vsc_psr { > #define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2) > = > static inline int > -drm_dp_max_link_rate(u8 dpcd[DP_RECEIVER_CAP_SIZE]) > +drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) > { > return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); > } > = > static inline u8 > -drm_dp_max_lane_count(u8 dpcd[DP_RECEIVER_CAP_SIZE]) > +drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) > { > return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; > } > -- = > 1.7.10.4 > = > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/dri-devel -- = Ville Syrj=E4l=E4 Intel OTC