Re: NUMA processor numbering

[Stephan von Krawczynski <skraw@ithnet.com>]

On Thu, 3 Oct 2013 07:22:55 -0300
Henrique de Moraes Holschuh <hmh@hmh.eng.br> wrote:

> On Thu, 03 Oct 2013, Stephan von Krawczynski wrote:
> > Does the above output mean that the cores are numbered right across the two
> > physical cpus? Does this mean one has to pin processes to 0,2,4,... to stay in
> > "short distance" to node 0 RAM?
> 
> ...
> 
> > If so, it would be a lot better to have them numbered 0-15 and 16-31 for pinning.
> > Is there a way to achieve this?
> 
> Yes, use hwloc to get the pinning masks for whatever property you want (e.g.
> all threads in a given core, all threads in a given node, all threads that
> share a given L3 cache...).
> 
> http://www.open-mpi.org/projects/hwloc/

Ok, let me re-phrase the question a bit.
Is it really possible what you see here:

processor       : 0
vendor_id       : GenuineIntel
cpu family      : 6
model           : 45
model name      : Intel(R) Xeon(R) CPU E5-2660 0 @ 2.20GHz
stepping        : 7
microcode       : 0x70d
cpu MHz         : 2002.000
cache size      : 20480 KB
physical id     : 0
siblings        : 16
core id         : 0
cpu cores       : 8
apicid          : 0
initial apicid  : 0
[...]

processor       : 1
vendor_id       : GenuineIntel
cpu family      : 6
model           : 45
model name      : Intel(R) Xeon(R) CPU E5-2660 0 @ 2.20GHz
stepping        : 7
microcode       : 0x70d
cpu MHz         : 1518.000
cache size      : 20480 KB
physical id     : 1
siblings        : 16
core id         : 0
cpu cores       : 8
apicid          : 32
initial apicid  : 32
[...]

These are the first two in the cpu list. If you look at that they are both on
core id 0, but have different physical ids. Up to now I thought that processor
1 is the HT of core id 0. But with a different physical id this would mean
that they are different NUMA nodes, right? How can that be? Someone from Intel
with a hint?

-- 
Regards,
Stephan