[U-Boot] [PATCH v2] arm: vf610: initial integration for colibri vf50

[Albert ARIBAUD <albert.u.boot@aribaud.net>]

Hi Marcel,

On Mon, 30 Sep 2013 14:57:12 +0200, Marcel Ziswiler
<marcel@ziswiler.com> wrote:

> Add initial Colibri VF50 support based off Freescale's implementation
> for the Vybrid Tower System TWR-VF65GS10:
> - New machine ID.
> - Default UART_A on SCI0.
> - FEC1 only.
> - Enabled command line editing.
> - PLL5 based RMII clocking (e.g. no external crystal).
> - UART_A and UART_C I/O muxing.
> 
> Tested on early Colibri VF50 prototypes V1.0a booting off SD card
> (mandatory for initial loading). Loading Linux kernel off SD card or by
> TFTP.
> 
> Changes v2:
> - Boot off gfxRAM rather than sysRAM0 to increase available space.
> - Fixed board string previously just copied from Tower.

Note: changes should not appear in the commit message; they should go
below the commit message delimiter '---'. 

> Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
> ---
>  board/toradex/colibri_vf50/Makefile       |   26 ++
>  board/toradex/colibri_vf50/colibri_vf50.c |  413 +++++++++++++++++++++++++++++
>  board/toradex/colibri_vf50/imximage.cfg   |   17 ++
>  boards.cfg                                |    1 +
>  include/configs/colibri_vf50.h            |  224 ++++++++++++++++
>  5 files changed, 681 insertions(+)
>  create mode 100644 board/toradex/colibri_vf50/Makefile
>  create mode 100644 board/toradex/colibri_vf50/colibri_vf50.c
>  create mode 100644 board/toradex/colibri_vf50/imximage.cfg
>  create mode 100644 include/configs/colibri_vf50.h
> 
> diff --git a/board/toradex/colibri_vf50/Makefile b/board/toradex/colibri_vf50/Makefile
> new file mode 100644
> index 0000000..43d21ab
> --- /dev/null
> +++ b/board/toradex/colibri_vf50/Makefile
> @@ -0,0 +1,26 @@
> +#
> +# Copyright 2013 Toradex, Inc.
> +#
> +# SPDX-License-Identifier:	GPL-2.0+
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB	= $(obj)lib$(BOARD).o
> +
> +COBJS	:= $(BOARD).o
> +
> +SRCS	:= $(COBJS:.o=.c)
> +OBJS	:= $(addprefix $(obj),$(COBJS))
> +
> +$(LIB):	$(obj).depend $(OBJS)
> +	$(call cmd_link_o_target, $(OBJS))
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/board/toradex/colibri_vf50/colibri_vf50.c b/board/toradex/colibri_vf50/colibri_vf50.c
> new file mode 100644
> index 0000000..83b6a67
> --- /dev/null
> +++ b/board/toradex/colibri_vf50/colibri_vf50.c
> @@ -0,0 +1,413 @@
> +/*
> + * Copyright 2013 Toradex, Inc.
> + *
> + * Based on vf610twr.c:
> + * Copyright 2013 Freescale Semiconductor, Inc.
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/arch/iomux-vf610.h>
> +#include <asm/arch/crm_regs.h>
> +#include <asm/arch/clock.h>
> +#include <mmc.h>
> +#include <fsl_esdhc.h>
> +#include <miiphy.h>
> +#include <netdev.h>
> +#include <i2c.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define UART_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
> +			PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
> +
> +#define ESDHC_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
> +			PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
> +
> +#define ENET_PAD_CTRL	(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
> +			PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
> +
> +void setup_iomux_ddr(void)
> +{
> +	static const iomux_v3_cfg_t ddr_pads[] = {
> +		VF610_PAD_DDR_A15__DDR_A_15,
> +		VF610_PAD_DDR_A14__DDR_A_14,
> +		VF610_PAD_DDR_A13__DDR_A_13,
> +		VF610_PAD_DDR_A12__DDR_A_12,
> +		VF610_PAD_DDR_A11__DDR_A_11,
> +		VF610_PAD_DDR_A10__DDR_A_10,
> +		VF610_PAD_DDR_A9__DDR_A_9,
> +		VF610_PAD_DDR_A8__DDR_A_8,
> +		VF610_PAD_DDR_A7__DDR_A_7,
> +		VF610_PAD_DDR_A6__DDR_A_6,
> +		VF610_PAD_DDR_A5__DDR_A_5,
> +		VF610_PAD_DDR_A4__DDR_A_4,
> +		VF610_PAD_DDR_A3__DDR_A_3,
> +		VF610_PAD_DDR_A2__DDR_A_2,
> +		VF610_PAD_DDR_A1__DDR_A_1,
> +		VF610_PAD_DDR_BA2__DDR_BA_2,
> +		VF610_PAD_DDR_BA1__DDR_BA_1,
> +		VF610_PAD_DDR_BA0__DDR_BA_0,
> +		VF610_PAD_DDR_CAS__DDR_CAS_B,
> +		VF610_PAD_DDR_CKE__DDR_CKE_0,
> +		VF610_PAD_DDR_CLK__DDR_CLK_0,
> +		VF610_PAD_DDR_CS__DDR_CS_B_0,
> +		VF610_PAD_DDR_D15__DDR_D_15,
> +		VF610_PAD_DDR_D14__DDR_D_14,
> +		VF610_PAD_DDR_D13__DDR_D_13,
> +		VF610_PAD_DDR_D12__DDR_D_12,
> +		VF610_PAD_DDR_D11__DDR_D_11,
> +		VF610_PAD_DDR_D10__DDR_D_10,
> +		VF610_PAD_DDR_D9__DDR_D_9,
> +		VF610_PAD_DDR_D8__DDR_D_8,
> +		VF610_PAD_DDR_D7__DDR_D_7,
> +		VF610_PAD_DDR_D6__DDR_D_6,
> +		VF610_PAD_DDR_D5__DDR_D_5,
> +		VF610_PAD_DDR_D4__DDR_D_4,
> +		VF610_PAD_DDR_D3__DDR_D_3,
> +		VF610_PAD_DDR_D2__DDR_D_2,
> +		VF610_PAD_DDR_D1__DDR_D_1,
> +		VF610_PAD_DDR_D0__DDR_D_0,
> +		VF610_PAD_DDR_DQM1__DDR_DQM_1,
> +		VF610_PAD_DDR_DQM0__DDR_DQM_0,
> +		VF610_PAD_DDR_DQS1__DDR_DQS_1,
> +		VF610_PAD_DDR_DQS0__DDR_DQS_0,
> +		VF610_PAD_DDR_RAS__DDR_RAS_B,
> +		VF610_PAD_DDR_WE__DDR_WE_B,
> +		VF610_PAD_DDR_ODT1__DDR_ODT_0,
> +		VF610_PAD_DDR_ODT0__DDR_ODT_1,
> +	};
> +
> +	imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
> +}
> +
> +void ddr_phy_init(void)
> +{
> +	struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
> +
> +	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]);

Do we need writel()s here? They should only be used when order of
writes matters.

> +	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]);
> +	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]);
> +	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[48]);
> +
> +	writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]);
> +	writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]);
> +	writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[33]);
> +	writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[49]);
> +
> +	writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]);
> +	writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]);
> +	writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]);
> +	writel(DDRMC_PHY_CTRL, &ddrmr->phy[50]);
> +
> +	writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]);
> +	writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]);
> +	writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]);
> +	writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[51]);
> +
> +	writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]);
> +	writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]);
> +	writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]);
> +	writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[52]);
> +
> +	writel(DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE,
> +		&ddrmr->phy[50]);
> +}
> +
> +void ddr_ctrl_init(void)
> +{
> +	struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
> +
> +	writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]);
> +	writel(DDRMC_CR02_DRAM_TINIT(32), &ddrmr->cr[2]);
> +	writel(DDRMC_CR10_TRST_PWRON(124), &ddrmr->cr[10]);
> +
> +	writel(DDRMC_CR11_CKE_INACTIVE(80000), &ddrmr->cr[11]);
> +	writel(DDRMC_CR12_WRLAT(5) | DDRMC_CR12_CASLAT_LIN(12), &ddrmr->cr[12]);
> +	writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4) |
> +		DDRMC_CR13_TBST_INT_INTERVAL(4), &ddrmr->cr[13]);
> +	writel(DDRMC_CR14_TFAW(20) | DDRMC_CR14_TRP(6) | DDRMC_CR14_TWTR(4) |
> +		DDRMC_CR14_TRAS_MIN(15), &ddrmr->cr[14]);
> +	writel(DDRMC_CR16_TMRD(4) | DDRMC_CR16_TRTP(4), &ddrmr->cr[16]);
> +	writel(DDRMC_CR17_TRAS_MAX(28080) | DDRMC_CR17_TMOD(12),
> +		&ddrmr->cr[17]);
> +	writel(DDRMC_CR18_TCKESR(4) | DDRMC_CR18_TCKE(3), &ddrmr->cr[18]);
> +
> +	writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]);
> +	writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_TRAS_LOCKOUT |
> +		DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]);
> +
> +	writel(DDRMC_CR22_TDAL(11), &ddrmr->cr[22]);
> +	writel(DDRMC_CR23_BSTLEN(3) | DDRMC_CR23_TDLL(512), &ddrmr->cr[23]);
> +	writel(DDRMC_CR24_TRP_AB(6), &ddrmr->cr[24]);
> +
> +	writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]);
> +	writel(DDRMC_CR26_TREF(3112) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]);
> +	writel(DDRMC_CR28_TREF_INT(5), &ddrmr->cr[28]);
> +	writel(DDRMC_CR29_TPDEX(3), &ddrmr->cr[29]);
> +
> +	writel(DDRMC_CR30_TXPDLL(10), &ddrmr->cr[30]);
> +	writel(DDRMC_CR31_TXSNR(68) | DDRMC_CR31_TXSR(512), &ddrmr->cr[31]);
> +	writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]);
> +	writel(DDRMC_CR34_CKSRX(5) | DDRMC_CR34_CKSRE(5), &ddrmr->cr[34]);
> +
> +	writel(DDRMC_CR38_FREQ_CHG_EN, &ddrmr->cr[38]);
> +	writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) |
> +		DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);
> +
> +	writel(DDRMC_CR41_PHY_INI_STRT_INI_DIS, &ddrmr->cr[41]);
> +	writel(DDRMC_CR48_MR1_DA_0(70) | DDRMC_CR48_MR0_DA_0(1056),
> +		&ddrmr->cr[48]);
> +
> +	writel(DDRMC_CR66_ZQCL(256) | DDRMC_CR66_ZQINIT(512), &ddrmr->cr[66]);
> +	writel(DDRMC_CR67_ZQCS(64), &ddrmr->cr[67]);
> +	writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);
> +
> +	writel(DDRMC_CR70_REF_PER_ZQ(64), &ddrmr->cr[70]);
> +	writel(DDRMC_CR72_ZQCS_ROTATE, &ddrmr->cr[72]);
> +
> +	writel(DDRMC_CR73_APREBIT(10) | DDRMC_CR73_COL_DIFF(1) |
> +		DDRMC_CR73_ROW_DIFF(3), &ddrmr->cr[73]);
> +	writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN |
> +		DDRMC_CR74_CMD_AGE_CNT(255) | DDRMC_CR74_AGE_CNT(255),
> +		&ddrmr->cr[74]);
> +	writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN |
> +		DDRMC_CR75_PLEN, &ddrmr->cr[75]);
> +	writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) |
> +		DDRMC_CR76_W2R_SPLT_EN | DDRMC_CR76_CS_EN, &ddrmr->cr[76]);
> +	writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE |
> +		DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
> +	writel(DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
> +	writel(DDRMC_CR79_CTLUPD_AREF, &ddrmr->cr[79]);
> +
> +	writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
> +
> +	writel(DDRMC_CR87_ODT_WR_MAPCS0 | DDRMC_CR87_ODT_RD_MAPCS0,
> +		&ddrmr->cr[87]);
> +	writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]);
> +	writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);
> +
> +	writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]);
> +	writel(DDRMC_CR96_WLMRD(40) | DDRMC_CR96_WLDQSEN(25), &ddrmr->cr[96]);
> +
> +	writel(DDRMC_CR105_RDLVL_DL_0(32), &ddrmr->cr[105]);
> +	writel(DDRMC_CR110_RDLVL_DL_1(32), &ddrmr->cr[110]);
> +	writel(DDRMC_CR114_RDLVL_GTDL_2(8224), &ddrmr->cr[114]);
> +
> +	writel(DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1),
> +		&ddrmr->cr[117]);
> +	writel(DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1),
> +		&ddrmr->cr[118]);
> +
> +	writel(DDRMC_CR120_AXI0_PRI1_RPRI(2) | DDRMC_CR120_AXI0_PRI0_RPRI(2),
> +		&ddrmr->cr[120]);
> +	writel(DDRMC_CR121_AXI0_PRI3_RPRI(2) | DDRMC_CR121_AXI0_PRI2_RPRI(2),
> +		&ddrmr->cr[121]);
> +	writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
> +		DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]);
> +	writel(DDRMC_CR123_AXI1_PRI3_RPRI(1) | DDRMC_CR123_AXI1_PRI2_RPRI(1),
> +		&ddrmr->cr[123]);
> +	writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]);
> +
> +	writel(DDRMC_CR126_PHY_RDLAT(11), &ddrmr->cr[126]);
> +	writel(DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6),
> +		&ddrmr->cr[132]);
> +	writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
> +		DDRMC_CR139_PHY_WRLV_DLL(3) | DDRMC_CR139_PHY_WRLV_EN(3),
> +		&ddrmr->cr[139]);
> +
> +	writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
> +		DDRMC_CR154_PAD_ZQ_MODE(1), &ddrmr->cr[154]);
> +	writel(DDRMC_CR155_AXI0_AWCACHE | DDRMC_CR155_PAD_ODT_BYTE1(2),
> +		&ddrmr->cr[155]);
> +	writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]);
> +
> +	ddr_phy_init();
> +
> +	writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
> +
> +	udelay(200);

Please add a comment explaining the reason for this delay and its
duration.

> +}
> +
> +int dram_init(void)
> +{
> +	setup_iomux_ddr();
> +
> +	ddr_ctrl_init();
> +	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
> +
> +	return 0;
> +}
> +
> +static void setup_iomux_uart(void)
> +{
> +	static const iomux_v3_cfg_t uart_pads[] = {
> +		NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL),	/* UART_C_TXD: SCI1_TX */
> +		NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL),	/* UART_C_RXD: SCI1_RX */
> +		NEW_PAD_CTRL(VF610_PAD_PTB10__UART0_TX, UART_PAD_CTRL),	/* UART_A_TXD: SCI0_TX */
> +		NEW_PAD_CTRL(VF610_PAD_PTB11__UART0_RX, UART_PAD_CTRL),	/* UART_A_RXD: SCI0_RX */
> +	};
> +
> +	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
> +}
> +
> +static void setup_iomux_enet(void)
> +{
> +	static const iomux_v3_cfg_t enet0_pads[] = {
> +		NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKOUT, ENET_PAD_CTRL),
> +		NEW_PAD_CTRL(VF610_PAD_PTC10__RMII1_MDIO, ENET_PAD_CTRL),
> +		NEW_PAD_CTRL(VF610_PAD_PTC9__RMII1_MDC, ENET_PAD_CTRL),
> +		NEW_PAD_CTRL(VF610_PAD_PTC11__RMII1_CRS_DV, ENET_PAD_CTRL),
> +		NEW_PAD_CTRL(VF610_PAD_PTC12__RMII1_RD1, ENET_PAD_CTRL),
> +		NEW_PAD_CTRL(VF610_PAD_PTC13__RMII1_RD0, ENET_PAD_CTRL),
> +		NEW_PAD_CTRL(VF610_PAD_PTC14__RMII1_RXER, ENET_PAD_CTRL),
> +		NEW_PAD_CTRL(VF610_PAD_PTC15__RMII1_TD1, ENET_PAD_CTRL),
> +		NEW_PAD_CTRL(VF610_PAD_PTC16__RMII1_TD0, ENET_PAD_CTRL),
> +		NEW_PAD_CTRL(VF610_PAD_PTC17__RMII1_TXEN, ENET_PAD_CTRL),
> +	};
> +
> +	imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
> +}
> +
> +static void setup_iomux_i2c(void)
> +{
> +	static const iomux_v3_cfg_t i2c0_pads[] = {
> +		VF610_PAD_PTB14__I2C0_SCL,
> +		VF610_PAD_PTB15__I2C0_SDA,
> +	};
> +
> +	imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads));
> +}
> +
> +#ifdef CONFIG_FSL_ESDHC
> +struct fsl_esdhc_cfg esdhc_cfg[1] = {
> +	{ESDHC1_BASE_ADDR},
> +};
> +
> +int board_mmc_getcd(struct mmc *mmc)
> +{
> +	/* eSDHC1 is always present */
> +	return 1;
> +}
> +
> +int board_mmc_init(bd_t *bis)
> +{
> +	static const iomux_v3_cfg_t esdhc1_pads[] = {
> +		NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
> +		NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
> +		NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
> +		NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
> +		NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
> +		NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
> +	};
> +
> +	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
> +
> +	imx_iomux_v3_setup_multiple_pads(
> +		esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
> +
> +	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
> +}
> +#endif
> +
> +static void clock_init(void)
> +{
> +	struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
> +	struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
> +
> +	clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
> +		CCM_CCGR0_UART0_CTRL_MASK);
> +	clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
> +		CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
> +	clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
> +		CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
> +		CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
> +		CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK);
> +	clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
> +		CCM_CCGR3_ANADIG_CTRL_MASK);
> +	clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
> +		CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
> +		CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
> +	clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
> +		CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
> +	clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
> +		CCM_CCGR7_SDHC1_CTRL_MASK);
> +	clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
> +		CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
> +
> +	clrsetbits_le32(&anadig->pll5_ctrl, ANADIG_PLL5_CTRL_BYPASS |
> +		ANADIG_PLL5_CTRL_POWERDOWN, ANADIG_PLL5_CTRL_ENABLE |
> +		ANADIG_PLL5_CTRL_DIV_SELECT);
> +	clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
> +		ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
> +	clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
> +		ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
> +
> +	clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
> +		CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
> +	clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
> +		CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN |
> +		CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
> +		CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN |
> +		CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
> +		CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) |
> +		CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
> +	clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
> +		CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
> +		CCM_CACRR_ARM_CLK_DIV(0));
> +	clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
> +		CCM_CSCMR1_ESDHC1_CLK_SEL(3));
> +	clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
> +		CCM_CSCDR1_RMII_CLK_EN);
> +	clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
> +		CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0));
> +	clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
> +		CCM_CSCMR2_RMII_CLK_SEL(2));	/* PLL5 main clock */
> +}
> +
> +static void mscm_init(void)
> +{
> +	struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
> +	int i;
> +
> +	for (i = 0; i < MSCM_IRSPRC_NUM; i++)
> +		writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
> +}
> +
> +int board_phy_config(struct phy_device *phydev)
> +{
> +	if (phydev->drv->config)
> +		phydev->drv->config(phydev);
> +
> +	return 0;
> +}
> +
> +int board_early_init_f(void)
> +{
> +	clock_init();
> +	mscm_init();
> +
> +	setup_iomux_uart();
> +	setup_iomux_enet();
> +	setup_iomux_i2c();
> +
> +	return 0;
> +}
> +
> +int board_init(void)
> +{
> +	/* address of boot parameters */
> +	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
> +
> +	return 0;
> +}
> +
> +int checkboard(void)
> +{
> +	puts("Board: Colibri VF50\n");
> +
> +	return 0;
> +}
> diff --git a/board/toradex/colibri_vf50/imximage.cfg b/board/toradex/colibri_vf50/imximage.cfg
> new file mode 100644
> index 0000000..c4369d6
> --- /dev/null
> +++ b/board/toradex/colibri_vf50/imximage.cfg
> @@ -0,0 +1,17 @@
> +/*
> + * Copyright 2013 Toradex, Inc.
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + *
> + * Refer docs/README.imxmage for more details about how-to configure
> + * and create imximage boot image
> + *
> + * The syntax is taken as close as possible with the kwbimage
> + */
> +#include <asm/imx-common/imximage.cfg>
> +
> +/* image version */
> +IMAGE_VERSION	2
> +
> +/* Boot Offset 0x400, valid for both SD and NAND boot */
> +BOOT_OFFSET	FLASH_OFFSET_STANDARD
> diff --git a/boards.cfg b/boards.cfg
> index 80846c9..7e037ed 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -342,6 +342,7 @@ Active  arm         armv7          socfpga     altera          socfpga
>  Active  arm         armv7          u8500       st-ericsson     snowball            snowball                             -                                                                                                                                 Mathieu Poirier <mathieu.poirier@linaro.org>
>  Active  arm         armv7          u8500       st-ericsson     u8500               u8500_href                           -                                                                                                                                 -
>  Active  arm         armv7          vf610       freescale       vf610twr            vf610twr                             vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg                                                                         Alison Wang <b18965@freescale.com>
> +Active  arm         armv7          vf610       toradex         colibri_vf50        colibri_vf50                         colibri_vf50:IMX_CONFIG=board/toradex/colibri_vf50/imximage.cfg                                                                   Marcel Ziswiler <marcel@ziswiler.com>
>  Active  arm         armv7          zynq        xilinx          zynq                zynq                                 -                                                                                                                                 Michal Simek <monstr@monstr.eu>
>  Active  arm         armv7          zynq        xilinx          zynq                zynq_dcc                             zynq:ZYNQ_DCC                                                                                                                     Michal Simek <monstr@monstr.eu>
>  Active  arm         armv7:arm720t  tegra114    nvidia          dalmore             dalmore                              -                                                                                                                                 Tom Warren <twarren@nvidia.com>
> diff --git a/include/configs/colibri_vf50.h b/include/configs/colibri_vf50.h
> new file mode 100644
> index 0000000..21e4e8d
> --- /dev/null
> +++ b/include/configs/colibri_vf50.h
> @@ -0,0 +1,224 @@
> +/*
> + * Copyright 2013 Toradex, Inc.
> + *
> + * Configuration settings for the Toradex VF50 module.
> + *
> + * Based on vf610twr.h:
> + * Copyright 2013 Freescale Semiconductor, Inc.
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#include <asm/arch/imx-regs.h>
> +#include <config_cmd_default.h>
> +
> +#define CONFIG_VF610
> +
> +#define CONFIG_DISPLAY_CPUINFO
> +#define CONFIG_DISPLAY_BOARDINFO
> +
> +#define CONFIG_MACH_TYPE		4749
> +
> +#define CONFIG_SKIP_LOWLEVEL_INIT
> +
> +/* Enable passing of ATAGs */
> +#define CONFIG_CMDLINE_TAG
> +
> +#define CONFIG_CMD_FUSE
> +#ifdef CONFIG_CMD_FUSE
> +#define CONFIG_MXC_OCOTP
> +#endif
> +
> +/* Size of malloc() pool */
> +#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
> +
> +#define CONFIG_BOARD_EARLY_INIT_F
> +
> +#define CONFIG_FSL_LPUART
> +#define LPUART_BASE			UART0_BASE
> +
> +/* Allow to overwrite serial and ethaddr */
> +#define CONFIG_ENV_OVERWRITE
> +#define CONFIG_BAUDRATE			115200
> +
> +#undef CONFIG_CMD_IMLS
> +
> +#define CONFIG_MMC
> +#define CONFIG_FSL_ESDHC
> +#define CONFIG_SYS_FSL_ESDHC_ADDR	0
> +#define CONFIG_SYS_FSL_ESDHC_NUM	1
> +
> +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
> +
> +#define CONFIG_CMD_MMC
> +#define CONFIG_GENERIC_MMC
> +#define CONFIG_CMD_FAT
> +#define CONFIG_DOS_PARTITION
> +
> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_MII
> +#define CONFIG_CMD_NET
> +#define CONFIG_FEC_MXC
> +#define CONFIG_MII
> +#define IMX_FEC_BASE			ENET1_BASE_ADDR
> +#define CONFIG_FEC_XCV_TYPE		RMII
> +#define CONFIG_FEC_MXC_PHYADDR          0
> +#define CONFIG_PHYLIB
> +#define CONFIG_PHY_MICREL
> +
> +/* I2C Configs */
> +#define CONFIG_CMD_I2C
> +#define CONFIG_HARD_I2C
> +#define CONFIG_I2C_MXC
> +#define CONFIG_SYS_I2C_BASE		I2C0_BASE_ADDR
> +#define CONFIG_SYS_I2C_SPEED		100000
> +
> +#define CONFIG_BOOTDELAY		3
> +
> +#define CONFIG_LOADADDR			0x82000000
> +#define CONFIG_SYS_TEXT_BASE		0x3f408000
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> +	"script=boot.scr\0" \
> +	"uimage=uImage\0" \
> +	"console=ttyLP0\0" \
> +	"fdt_high=0xffffffff\0" \
> +	"initrd_high=0xffffffff\0" \
> +	"fdt_file=colibri_vf50.dtb\0" \
> +	"fdt_addr=0x81000000\0" \
> +	"boot_fdt=try\0" \
> +	"ip_dyn=yes\0" \
> +	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
> +	"mmcpart=1\0" \
> +	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
> +	"update_sd_firmware_filename=u-boot.imx\0" \
> +	"update_sd_firmware=" \
> +		"if test ${ip_dyn} = yes; then " \
> +			"setenv get_cmd dhcp; " \
> +		"else " \
> +			"setenv get_cmd tftp; " \
> +		"fi; " \
> +		"if mmc dev ${mmcdev}; then "	\
> +			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
> +				"setexpr fw_sz ${filesize} / 0x200; " \
> +				"setexpr fw_sz ${fw_sz} + 1; "	\
> +				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
> +			"fi; "	\
> +		"fi\0" \
> +	"mmcargs=setenv bootargs console=${console},${baudrate} " \
> +		"root=${mmcroot}\0" \
> +	"loadbootscript=" \
> +		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
> +	"bootscript=echo Running bootscript from mmc ...; " \
> +		"source\0" \
> +	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
> +	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
> +	"mmcboot=echo Booting from mmc ...; " \
> +		"run mmcargs; " \
> +		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
> +			"if run loadfdt; then " \
> +				"bootm ${loadaddr} - ${fdt_addr}; " \
> +			"else " \
> +				"if test ${boot_fdt} = try; then " \
> +					"bootm; " \
> +				"else " \
> +					"echo WARN: Cannot load the DT; " \
> +				"fi; " \
> +			"fi; " \
> +		"else " \
> +			"bootm; " \
> +		"fi;\0" \
> +	"netargs=setenv bootargs console=${console},${baudrate} " \
> +		"root=/dev/nfs " \
> +	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
> +		"netboot=echo Booting from net ...; " \
> +		"run netargs; " \
> +		"if test ${ip_dyn} = yes; then " \
> +			"setenv get_cmd dhcp; " \
> +		"else " \
> +			"setenv get_cmd tftp; " \
> +		"fi; " \
> +		"${get_cmd} ${uimage}; " \
> +		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
> +			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
> +				"bootm ${loadaddr} - ${fdt_addr}; " \
> +			"else " \
> +				"if test ${boot_fdt} = try; then " \
> +					"bootm; " \
> +				"else " \
> +					"echo WARN: Cannot load the DT; " \
> +				"fi; " \
> +			"fi; " \
> +		"else " \
> +			"bootm; " \
> +		"fi;\0"
> +
> +#define CONFIG_BOOTCOMMAND \
> +	   "mmc dev ${mmcdev}; if mmc rescan; then " \
> +		   "if run loadbootscript; then " \
> +			   "run bootscript; " \
> +		   "else " \
> +			   "if run loaduimage; then " \
> +				   "run mmcboot; " \
> +			   "else run netboot; " \
> +			   "fi; " \
> +		   "fi; " \
> +	   "else run netboot; fi"
> +
> +/* Miscellaneous configurable options */
> +#define CONFIG_SYS_LONGHELP		/* undef to save memory */
> +#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
> +#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
> +#define CONFIG_SYS_PROMPT		"=> "
> +#undef CONFIG_AUTO_COMPLETE
> +#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
> +#define CONFIG_SYS_PBSIZE		\
> +			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
> +#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
> +#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
> +
> +#define CONFIG_CMD_MEMTEST
> +#define CONFIG_SYS_MEMTEST_START	0x80010000
> +#define CONFIG_SYS_MEMTEST_END		0x87C00000
> +
> +#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
> +#define CONFIG_SYS_HZ			1000
> +#define CONFIG_CMDLINE_EDITING
> +
> +/*
> + * Stack sizes
> + * The stack sizes are set up in start.S using the settings below
> + */
> +#define CONFIG_STACKSIZE		(128 * 1024)	/* regular stack */
> +
> +/* Physical memory map */
> +#define CONFIG_NR_DRAM_BANKS		1
> +#define PHYS_SDRAM			(0x80000000)
> +#define PHYS_SDRAM_SIZE			(128 * 1024 * 1024)
> +
> +#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
> +#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
> +#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
> +
> +#define CONFIG_SYS_INIT_SP_OFFSET \
> +	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_ADDR \
> +	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> +
> +/* FLASH and environment organization */
> +#define CONFIG_SYS_NO_FLASH
> +
> +#define CONFIG_ENV_SIZE			(8 * 1024)
> +#define CONFIG_ENV_IS_IN_MMC
> +
> +#define CONFIG_ENV_OFFSET		(12 * 64 * 1024)
> +#define CONFIG_SYS_MMC_ENV_DEV		0
> +
> +#define CONFIG_OF_LIBFDT
> +#define CONFIG_CMD_BOOTZ
> +
> +#endif


Amicalement,
-- 
Albert.