From: Christoffer Dall <christoffer.dall@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: Patch Tracking <patches@linaro.org>,
QEMU Developers <qemu-devel@nongnu.org>,
"kvmarm@lists.cs.columbia.edu" <kvmarm@lists.cs.columbia.edu>
Subject: Re: [Qemu-devel] [RFC PATCH v2 3/6] hw: arm_gic: Keep track of SGI sources
Date: Wed, 23 Oct 2013 16:50:57 +0100 [thread overview]
Message-ID: <20131023155057.GC60827@lvm> (raw)
In-Reply-To: <CAFEAcA-zDJK6PD8SL+Xyt=4a0Jk+S0WntMFuaesePOqzmjC9Pg@mail.gmail.com>
On Mon, Oct 14, 2013 at 05:33:38PM +0100, Peter Maydell wrote:
> On 14 October 2013 16:36, Peter Maydell <peter.maydell@linaro.org> wrote:
[...]
>
> Tangentially, I notice that we don't correctly handle
> the PENDING bit for level triggered interrupts, since
> we do:
>
> /* Clear pending flags for both level and edge triggered interrupts.
> Level triggered IRQs will be reasserted once they become inactive. */
> gic_clear_pending(s, new_irq, GIC_TEST_MODEL(new_irq) ? ALL_CPU_MASK : cm,
> GIC_SGI_SRC(new_irq, cpu));
>
> in gic_acknowledge_irq(). This is wrong, because section
> 3.2.4 is clear for a level triggered interrupt that if the
> interrupt signal remains asserted (which it usually will be)
> then we go from Pending to Active+Pending (whereas our
> current implementation goes from Pending to Active and
> then resets Pending later in gic_complete_irq()).
>
Yes, I will send this patch to address this as part of the revised series:
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index bf1eb02..fce66c6 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -175,10 +180,15 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu)
return 1023;
}
s->last_active[new_irq][cpu] = s->running_irq[cpu];
- /* Clear pending flags for both level and edge triggered interrupts.
- Level triggered IRQs will be reasserted once they become inactive. */
- gic_clear_pending(s, new_irq, GIC_TEST_MODEL(new_irq) ? ALL_CPU_MASK : cm,
- GIC_SGI_SRC(new_irq, cpu));
+ /* Clear pending flags for edge-triggered and non-asserted level-triggered
+ * interrupts.
+ */
+ cm = GIC_TEST_MODEL(new_irq) ? ALL_CPU_MASK : cm;
+ if (GIC_TEST_TRIGGER(new_irq) || !GIC_TEST_LEVEL(new_irq, cm)) {
+ gic_clear_pending(s, new_irq, cm, GIC_SGI_SRC(new_irq, cpu));
+ }
+
gic_set_running_irq(s, cpu, new_irq);
DPRINTF("ACK %d\n", new_irq);
return new_irq;
--
Christoffer
next prev parent reply other threads:[~2013-10-23 15:51 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-09-26 21:03 [Qemu-devel] [RFC PATCH v2 0/6] Support arm-gic-kvm save/restore Christoffer Dall
2013-09-26 21:03 ` [Qemu-devel] [RFC PATCH v2 1/6] hw: arm_gic: Fix gic_set_irq handling Christoffer Dall
2013-10-14 14:24 ` Peter Maydell
2013-10-23 15:23 ` Christoffer Dall
2013-10-23 15:26 ` [Qemu-devel] [PATCH] arm_gic: Keep track of GICD_CPENDR and GICD_SPENDR Christoffer Dall
2013-10-29 16:10 ` Bhushan Bharat-R65777
2013-11-17 19:45 ` Christoffer Dall
2013-09-26 21:03 ` [Qemu-devel] [RFC PATCH v2 2/6] hw: arm_gic: Introduce GIC_SET_PRIORITY macro Christoffer Dall
2013-10-14 14:34 ` Peter Maydell
2013-09-26 21:03 ` [Qemu-devel] [RFC PATCH v2 3/6] hw: arm_gic: Keep track of SGI sources Christoffer Dall
2013-10-14 15:36 ` Peter Maydell
2013-10-14 16:33 ` Peter Maydell
2013-10-23 15:50 ` Christoffer Dall [this message]
2013-11-19 2:53 ` Christoffer Dall
2013-09-26 21:03 ` [Qemu-devel] [RFC PATCH v2 4/6] arm_gic: Support setting/getting binary point reg Christoffer Dall
2013-10-14 15:43 ` Peter Maydell
2013-09-26 21:03 ` [Qemu-devel] [RFC PATCH v2 5/6] vmstate: Add uint32 2D-array support Christoffer Dall
2013-10-14 15:44 ` Peter Maydell
2013-09-26 21:03 ` [Qemu-devel] [RFC PATCH v2 6/6] hw: arm_gic_kvm: Add KVM VGIC save/restore logic Christoffer Dall
2013-09-27 8:11 ` Alex Bennée
2013-10-15 10:35 ` Peter Maydell
2013-11-19 3:50 ` Christoffer Dall
2013-10-15 11:15 ` Peter Maydell
2013-11-19 4:17 ` Christoffer Dall
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