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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/3] drm/i915: move VLV DDR freq fetch into init_clock_gating
Date: Tue, 5 Nov 2013 00:49:57 +0200	[thread overview]
Message-ID: <20131104224957.GD13047@intel.com> (raw)
In-Reply-To: <1383594766-6042-2-git-send-email-jbarnes@virtuousgeek.org>

On Mon, Nov 04, 2013 at 11:52:45AM -0800, Jesse Barnes wrote:
> We don't want it delayed with the RPS work.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 31 ++++++++++++++++++-------------
>  1 file changed, 18 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index a0c907f..2e7072e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4064,19 +4064,6 @@ static void valleyview_enable_rps(struct drm_device *dev)
>  	I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
>  
>  	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> -	switch ((val >> 6) & 3) {
> -	case 0:
> -	case 1:
> -		dev_priv->mem_freq = 800;
> -		break;
> -	case 2:
> -		dev_priv->mem_freq = 1066;
> -		break;
> -	case 3:
> -		dev_priv->mem_freq = 1333;
> -		break;
> -	}
> -	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
>  
>  	DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
>  	DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
> @@ -5325,6 +5312,24 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
>  static void valleyview_init_clock_gating(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> +	u32 val;
> +
> +	mutex_lock(&dev_priv->rps.hw_lock);
> +	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> +	mutex_unlock(&dev_priv->rps.hw_lock);
> +	switch ((val >> 6) & 3) {
> +	case 0:
> +	case 1:
> +		dev_priv->mem_freq = 800;
> +		break;
> +	case 2:
> +		dev_priv->mem_freq = 1066;
> +		break;
> +	case 3:
> +		dev_priv->mem_freq = 1333;
> +		break;
> +	}

This doesn't actually match the punit HAS I have. What I see
is 0=800, 1=1066, 2=1333, 3=invalid.

But using the DDR rate to determine the CCK clock isn't the best idea
I think. It seems there's an option of running CCK at 800MHz even for
the DDR 1066 case. So I think we should just use CCK_FUSE_REG to
figure it out, just like gmbus_set_freq() already does.

> +	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
>  
>  	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
>  
> -- 
> 1.8.3.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC

  reply	other threads:[~2013-11-04 22:50 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-11-04 19:52 [PATCH 1/3] drm/i915: add bunit read/write routines Jesse Barnes
2013-11-04 19:52 ` [PATCH 2/3] drm/i915: move VLV DDR freq fetch into init_clock_gating Jesse Barnes
2013-11-04 22:49   ` Ville Syrjälä [this message]
2013-11-05  0:01     ` Jesse Barnes
2013-11-04 19:52 ` [PATCH 3/3] drm/i915/vlv: modeset_global_* for VLV v5 Jesse Barnes
2013-11-04 20:37   ` Ville Syrjälä
2013-11-04 20:54   ` [PATCH] drm/i915/vlv: modeset_global_* for VLV v6 Jesse Barnes
2013-11-04 21:22     ` Ville Syrjälä
2013-11-04 21:24       ` Jesse Barnes
2013-11-04 21:28       ` Ville Syrjälä
2013-11-04 21:48     ` [PATCH] drm/i915/vlv: modeset_global_* for VLV v7 Jesse Barnes
2013-11-04 22:27       ` Ville Syrjälä
  -- strict thread matches above, loose matches on Subject: below --
2013-10-28 20:46 [PATCH 1/3] drm/i915: add bunit read/write routines Jesse Barnes
2013-10-28 20:46 ` [PATCH 2/3] drm/i915: move VLV DDR freq fetch into init_clock_gating Jesse Barnes
2013-10-28 18:14 [PATCH 1/3] drm/i915: add bunit read/write routines Jesse Barnes
2013-10-28 18:14 ` [PATCH 2/3] drm/i915: move VLV DDR freq fetch into init_clock_gating Jesse Barnes

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