From mboxrd@z Thu Jan  1 00:00:00 1970
From: Alex Hacker <hacker@epn.ru>
Date: Tue, 12 Nov 2013 12:49:07 +0600
Subject: [ath9k-devel] ath9k: set 5/10 MHz supported channels
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Hello,
I'm not ath9k developer, obviously I work with Atheros and QCA chips in non
open source conditions, so I havn't a code to publish. What I can do for you it
is a several hints about HW.
Yes, you are in the right way, 5/10 MHz bandwidth controlled by AR_PHY_MODE
register and changes the PLL frequency. In the code I see what almost all
required work is already done. You should dig yourself into the higher layers
of code to understand how to do it at the user level.
At the end I should say that these bandwidths is not conform to IEEE802.11 and
ETSI/FCC policies so it actually illegal.
Alex.