Re: Problem reading and programming memory location...

[Anatolij Gustschin <agust@denx.de>]

Hi Lorenzo,

On Tue, 19 Nov 2013 11:20:24 +0100
neorf3k <neorf3k@gmail.com> wrote:

> Hello Anatolij, this is our code, used at University, but again it doesn=
=E2=80=99t work=E2=80=A6
>=20
> How i told, the only information we have about that reg are:
>=20
> Chip select 4 specification:
> Lp_cs4
> bus size: 8 bit
> bus control: 2 wait state R/W ACK disabled
> size allocated: 4 KByte
>=20
> Our Register 8 bit LP_cs4 (we want to write)
>=20
> cs4 offset: 0x001

is the byte in FPGA at offset 0x0 writable? In your code you
currently test read/write access to the byte at offset 0x0.

If the read/write access works under U-Boot, then maybe the
chip select parameters for CS4 are configured differently
in U-Boot. You can dump the Chip Select 4 configuration
registers under U-Boot and compare. Is address- and data-bus
to the FPGA multipexed? Another possible reason for non-working
access could be that the configured CS4 range 0x10020000 - 0x10030000
overlaps with configured range for CS0, CS1, CS2 or CS3. Can you
verify that no such overlapping exists.

Thanks,

Anatolij