From: Bjorn Helgaas <bhelgaas@google.com>
To: Jason Cooper <jason@lakedaemon.net>
Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>,
Thomas Petazzoni <thomas.petazzoni@free-electrons.com>,
Ezequiel Garcia <ezequiel.garcia@free-electrons.com>,
linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org
Subject: Re: [PATCH] PCI: mvebu - The bridge secondary status register should be 0
Date: Tue, 26 Nov 2013 11:38:34 -0700 [thread overview]
Message-ID: <20131126183834.GA12152@google.com> (raw)
In-Reply-To: <20131126182328.GP2879@titan.lakedaemon.net>
On Tue, Nov 26, 2013 at 01:23:28PM -0500, Jason Cooper wrote:
> On Tue, Nov 26, 2013 at 11:02:52AM -0700, Jason Gunthorpe wrote:
> > There are no writable bits in the secondary status register, only
> > write 1 to clear bits. The driver never sets any of the write 1 to
> > clear bits so the status register should always be 0, just remove
> > the set from the write path.
> >
> > Someday the write 1 to clear bits should be copied/cleared directly
> > from registers in the HW.
> >
> > Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
> > ---
> > drivers/pci/host/pci-mvebu.c | 1 -
> > 1 file changed, 1 deletion(-)
>
> Whole series
>
> Acked-by: Jason Cooper <jason@lakedaemon.net>
Thanks, I applied the Interrupt Line/Pin change to for-linus for v3.13, and
the others to pci/host-mvebu for v3.14.
Bjorn
WARNING: multiple messages have this Message-ID (diff)
From: bhelgaas@google.com (Bjorn Helgaas)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] PCI: mvebu - The bridge secondary status register should be 0
Date: Tue, 26 Nov 2013 11:38:34 -0700 [thread overview]
Message-ID: <20131126183834.GA12152@google.com> (raw)
In-Reply-To: <20131126182328.GP2879@titan.lakedaemon.net>
On Tue, Nov 26, 2013 at 01:23:28PM -0500, Jason Cooper wrote:
> On Tue, Nov 26, 2013 at 11:02:52AM -0700, Jason Gunthorpe wrote:
> > There are no writable bits in the secondary status register, only
> > write 1 to clear bits. The driver never sets any of the write 1 to
> > clear bits so the status register should always be 0, just remove
> > the set from the write path.
> >
> > Someday the write 1 to clear bits should be copied/cleared directly
> > from registers in the HW.
> >
> > Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
> > ---
> > drivers/pci/host/pci-mvebu.c | 1 -
> > 1 file changed, 1 deletion(-)
>
> Whole series
>
> Acked-by: Jason Cooper <jason@lakedaemon.net>
Thanks, I applied the Interrupt Line/Pin change to for-linus for v3.13, and
the others to pci/host-mvebu for v3.14.
Bjorn
next prev parent reply other threads:[~2013-11-26 18:38 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-11-26 18:02 [PATCH] PCI: mvebu - The bridge secondary status register should be 0 Jason Gunthorpe
2013-11-26 18:02 ` Jason Gunthorpe
2013-11-26 18:02 ` [PATCH] PCI: mvebu - Return a value for the INTERRUPT_LINE/PIN register Jason Gunthorpe
2013-11-26 18:02 ` Jason Gunthorpe
2013-11-26 18:02 ` [PATCH RESEND v3 1/2] PCI: mvebu - The bridge should obey the MEM and IO command bits Jason Gunthorpe
2013-11-26 18:02 ` Jason Gunthorpe
2013-11-26 18:02 ` [PATCH RESEND v3 2/2] PCI: mvebu - Support a bridge with no IO port window Jason Gunthorpe
2013-11-26 18:02 ` Jason Gunthorpe
2013-11-26 18:23 ` [PATCH] PCI: mvebu - The bridge secondary status register should be 0 Jason Cooper
2013-11-26 18:23 ` Jason Cooper
2013-11-26 18:38 ` Bjorn Helgaas [this message]
2013-11-26 18:38 ` Bjorn Helgaas
-- strict thread matches above, loose matches on Subject: below --
2013-10-15 20:16 Jason Gunthorpe
2013-10-15 20:16 ` Jason Gunthorpe
2013-10-17 13:12 ` Jason Cooper
2013-10-17 13:12 ` Jason Cooper
2013-10-31 8:54 ` Thomas Petazzoni
2013-10-31 8:54 ` Thomas Petazzoni
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