Re: [Qemu-devel] [PATCH for 1.7] target-mips: fix 64-bit FPU config for user-mode emulation

[Aurelien Jarno <aurelien@aurel32.net>]

On Fri, Nov 29, 2013 at 05:27:42PM +0100, Petar Jovanovic wrote:
> From: Petar Jovanovic <petar.jovanovic@imgtec.com>
> 
> FR bit should be initialized to 1 for MIPS64, under condition that this
> bit is writable and that CPU has an FPU unit. It should be initialized to
> zero for MIPS32.
> This fixes different MIPS32 issues with FPU instructions whose behaviour
> defaulted to 64-bit FPU mode.
> 
> Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
> ---
> 
> A few issues have been raised over the time because this part of the code
> did the wrong thing for MIPS32. This change is sufficient to fix the
> reported issues, such as https://bugs.launchpad.net/qemu/+bug/1233225.
> This change does not attempt to cover -mfp64 mode that should be
> subject of different yet related change.
> We should have this in v1.7 since it is a regression for frequently used
> QEMU MIPS32 usermode.
> 
>  target-mips/translate.c |    7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index 67f326b..e302734 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -15983,10 +15983,13 @@ void cpu_state_reset(CPUMIPSState *env)
>      if (env->CP0_Config3 & (1 << CP0C3_DSPP)) {
>          env->CP0_Status |= (1 << CP0St_MX);
>      }
> -    /* Enable 64-bit FPU if the target cpu supports it.  */
> -    if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
> +# if defined(TARGET_MIPS64)
> +    /* For MIPS64, init FR bit to 1 if FPU unit is there and bit is writable. */
> +    if ((env->CP0_Config1 & (1 << CP0C1_FP)) &&
> +        (env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) {
>          env->CP0_Status |= (1 << CP0St_FR);
>      }
> +# endif
>  #else
>      if (env->hflags & MIPS_HFLAG_BMASK) {
>          /* If the exception was raised from a delay slot,

Thanks, applied.


-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net