Re: [PATCH 1/2] PCI: Prevent bus conflicts while checking for bridge apertures

[Jason Gunthorpe <jgunthorpe@obsidianresearch.com>]

On Thu, Dec 05, 2013 at 05:19:47PM -0700, Bjorn Helgaas wrote:
> pci_bridge_check_ranges() determines whether the bridge supports an I/O
> aperture and a prefetchable memory aperture.
> 
> Previously, if the I/O aperture was unsupported, disabled, or configured at
> [io 0x0000-0x0fff], we wrote 0xf0 to PCI_IO_BASE and PCI_IO_LIMIT, which,
> if the bridge supports it, enables the I/O aperture at [io 0xf000-0xffff].
> The enabled aperture may conflict with other devices in the system.
> 
> Similarly, we wrote 0xfff0 to PCI_PREF_MEMORY_BASE and
> PCI_PREF_MEMORY_LIMIT, which enables the prefetchable memory aperture at
> [mem 0xfff00000-0xffffffff], and that may also conflict with other devices.
> 
> All we need to know is whether the base and limit registers are writable,
> so we can use values that leave the apertures disabled, e.g., PCI_IO_BASE =
> 0xf0, PCI_IO_LIMIT = 0xe0, PCI_PREF_MEMORY_BASE = 0xfff0,
> PCI_PREF_MEMORY_LIMIT = 0xffe0.
> 
> Writing non-zero values to both the base and limit registers means we
> detect whether either or both are writable, as we did before.

Looks sane to me. The only refinement would be to detect if IO is
enabled and use that as a first check.

Cheers,
Jason