diff for duplicates of <20131219123719.3226.44864.stgit@tamien> diff --git a/a/1.txt b/N1/1.txt index 3ce7a0c..8e27a45 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,12 +1,12 @@ Add basic DT bindings for the DFLL IP block for the NVIDIA Tegra114 SoC. -Signed-off-by: Paul Walmsley <pwalmsley-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> -Cc: Matthew Longnecker <mlongnecker-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> -Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> -Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org> -Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> -Cc: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org> -Cc: Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> +Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com> +Cc: Matthew Longnecker <mlongnecker@nvidia.com> +Cc: Rob Herring <robh+dt@kernel.org> +Cc: Pawel Moll <pawel.moll@arm.com> +Cc: Mark Rutland <mark.rutland@arm.com> +Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> +Cc: Kumar Gala <galak@codeaurora.org> --- .../bindings/clock/nvidia,tegra114-dfll.txt | 43 ++++++++++++++++++++ arch/arm/boot/dts/tegra114.dtsi | 10 +++++ @@ -52,7 +52,7 @@ index 000000000000..b868bf97bc3d + +Example: + -+dfll@70110000 { ++dfll at 70110000 { + compatible = "nvidia,tegra114-dfll-fcpu"; + reg = <0x70110000 0x400>; + clocks = <&tegra_car TEGRA114_CLK_DFLL_SOC>, @@ -70,7 +70,7 @@ index ae855ec60bbd..1cd59d79e67c 100644 }; }; -+ dfll@70110000 { ++ dfll at 70110000 { + compatible = "nvidia,tegra114-dfll-fcpu"; + reg = <0x70110000 0x400>; + clocks = <&tegra_car TEGRA114_CLK_DFLL_SOC>, @@ -80,11 +80,6 @@ index ae855ec60bbd..1cd59d79e67c 100644 + status = "disabled"; + }; + - sdhci@78000000 { + sdhci at 78000000 { compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; reg = <0x78000000 0x200>; - --- -To unsubscribe from this list: send the line "unsubscribe devicetree" in -the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org -More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index a4acda6..ee61934 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,27 +1,19 @@ "ref\020131219122857.3226.42830.stgit@tamien\0" - "From\0Paul Walmsley <pwalmsley-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\0" + "From\0pwalmsley@nvidia.com (Paul Walmsley)\0" "Subject\0[PATCH 4/6] ARM: DTS: tegra: add the DFLL IP block to the T114 SoC file\0" "Date\0Thu, 19 Dec 2013 04:49:22 -0800\0" - "To\0linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" - " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" - "Cc\0Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>" - devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org> - Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org> - Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> - Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> - " Matthew Longnecker <mlongnecker-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Add basic DT bindings for the DFLL IP block for the NVIDIA Tegra114 SoC.\n" "\n" - "Signed-off-by: Paul Walmsley <pwalmsley-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" - "Cc: Matthew Longnecker <mlongnecker-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" - "Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>\n" - "Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>\n" - "Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>\n" - "Cc: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>\n" - "Cc: Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>\n" + "Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com>\n" + "Cc: Matthew Longnecker <mlongnecker@nvidia.com>\n" + "Cc: Rob Herring <robh+dt@kernel.org>\n" + "Cc: Pawel Moll <pawel.moll@arm.com>\n" + "Cc: Mark Rutland <mark.rutland@arm.com>\n" + "Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>\n" + "Cc: Kumar Gala <galak@codeaurora.org>\n" "---\n" " .../bindings/clock/nvidia,tegra114-dfll.txt | 43 ++++++++++++++++++++\n" " arch/arm/boot/dts/tegra114.dtsi | 10 +++++\n" @@ -67,7 +59,7 @@ "+\n" "+Example:\n" "+\n" - "+dfll@70110000 {\n" + "+dfll at 70110000 {\n" "+ compatible = \"nvidia,tegra114-dfll-fcpu\";\n" "+ reg = <0x70110000 0x400>;\n" "+ clocks = <&tegra_car TEGRA114_CLK_DFLL_SOC>,\n" @@ -85,7 +77,7 @@ " \t\t};\n" " \t};\n" " \n" - "+\tdfll@70110000 {\n" + "+\tdfll at 70110000 {\n" "+\t\tcompatible = \"nvidia,tegra114-dfll-fcpu\";\n" "+\t\treg = <0x70110000 0x400>;\n" "+\t\tclocks = <&tegra_car TEGRA114_CLK_DFLL_SOC>,\n" @@ -95,13 +87,8 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - " \tsdhci@78000000 {\n" + " \tsdhci at 78000000 {\n" " \t\tcompatible = \"nvidia,tegra114-sdhci\", \"nvidia,tegra30-sdhci\";\n" - " \t\treg = <0x78000000 0x200>;\n" - "\n" - "--\n" - "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" - "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" - More majordomo info at http://vger.kernel.org/majordomo-info.html + " \t\treg = <0x78000000 0x200>;" -25c81984033f279f4f8f734cd09aaf248b1ab5fc52131ca86edc157aa5ad4eea +2b46ebeb2b6fde1e27d43891f28bca4c8aff5c3ed1f68d821c76d08a6491f944
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