From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58739) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VunOZ-0006ib-3l for qemu-devel@nongnu.org; Sun, 22 Dec 2013 13:05:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VunOU-0000VY-9b for qemu-devel@nongnu.org; Sun, 22 Dec 2013 13:04:55 -0500 Received: from hall.aurel32.net ([2001:bc8:30d7:101::1]:51888) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VunOU-0000VR-3B for qemu-devel@nongnu.org; Sun, 22 Dec 2013 13:04:50 -0500 Date: Sun, 22 Dec 2013 19:04:48 +0100 From: Aurelien Jarno Message-ID: <20131222180448.GF4326@ohm.rr44.fr> References: <1386366292-5340-1-git-send-email-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <1386366292-5340-1-git-send-email-rth@twiddle.net> Subject: Re: [Qemu-devel] [PATCH 1/2] cputlb: Use memset when flushing entries List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: qemu-devel@nongnu.org On Sat, Dec 07, 2013 at 10:44:51AM +1300, Richard Henderson wrote: > The size of tlb_table is 4k on a 64-bit host. For overwriting > memory at this size, cacheline tricks can help. > > Signed-off-by: Richard Henderson > --- > cputlb.c | 19 ++----------------- > 1 file changed, 2 insertions(+), 17 deletions(-) > > diff --git a/cputlb.c b/cputlb.c > index fff0afb..d2da404 100644 > --- a/cputlb.c > +++ b/cputlb.c > @@ -33,13 +33,6 @@ > /* statistics */ > int tlb_flush_count; > > -static const CPUTLBEntry s_cputlb_empty_entry = { > - .addr_read = -1, > - .addr_write = -1, > - .addr_code = -1, > - .addend = -1, > -}; > - > /* NOTE: > * If flush_global is true (the usual case), flush all tlb entries. > * If flush_global is false, flush (at least) all tlb entries not > @@ -55,7 +48,6 @@ static const CPUTLBEntry s_cputlb_empty_entry = { > void tlb_flush(CPUArchState *env, int flush_global) > { > CPUState *cpu = ENV_GET_CPU(env); > - int i; > > #if defined(DEBUG_TLB) > printf("tlb_flush:\n"); > @@ -64,14 +56,7 @@ void tlb_flush(CPUArchState *env, int flush_global) > links while we are modifying them */ > cpu->current_tb = NULL; > > - for (i = 0; i < CPU_TLB_SIZE; i++) { > - int mmu_idx; > - > - for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { > - env->tlb_table[mmu_idx][i] = s_cputlb_empty_entry; > - } > - } > - > + memset(env->tlb_table, -1, sizeof(env->tlb_table)); > memset(env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); > > env->tlb_flush_addr = -1; > @@ -87,7 +72,7 @@ static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr) > (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || > addr == (tlb_entry->addr_code & > (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { > - *tlb_entry = s_cputlb_empty_entry; > + memset(tlb_entry, -1, sizeof(*tlb_entry)); > } > } Reviewed-by: Aurelien Jarno -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net