From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54279) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vv6o3-0007mX-4h for qemu-devel@nongnu.org; Mon, 23 Dec 2013 09:48:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Vv6nv-00014b-O3 for qemu-devel@nongnu.org; Mon, 23 Dec 2013 09:48:31 -0500 Received: from mx1.redhat.com ([209.132.183.28]:12011) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vv6nv-00014X-Eq for qemu-devel@nongnu.org; Mon, 23 Dec 2013 09:48:23 -0500 Date: Mon, 23 Dec 2013 16:52:16 +0200 From: "Michael S. Tsirkin" Message-ID: <20131223145216.GA22663@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH v3] target-arm: fix build with gcc 4.8.2 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Alexander Graf , Richard Henderson commit 5ce4f35781028ce1aee3341e6002f925fdc7aaf3 "target-arm: A64: add set_pc cpu method" introduces an array aarch64_cpus which is zero size if this code is built without CONFIG_USER_ONLY. In particular an attempt to iterate over this array produces a warning under gcc 4.8.2: CC aarch64-softmmu/target-arm/cpu64.o /scm/qemu/target-arm/cpu64.c: In function =E2=80=98aarch64_cpu_register_t= ypes=E2=80=99: /scm/qemu/target-arm/cpu64.c:124:5: error: comparison of unsigned expression < 0 is always false [-Werror=3Dtype-limits] for (i =3D 0; i < ARRAY_SIZE(aarch64_cpus); i++) { ^ cc1: all warnings being treated as errors This is the result of ARRAY_SIZE being an unsigned type, causing "i" to be promoted to unsigned int as well. As zero size arrays are a gcc extension, it seems cleanest to add a dummy element with NULL name, and test for it during registration. We'll be able to drop this when we add more CPUs. Cc: Alexander Graf Cc: Peter Maydell Cc: Richard Henderson Signed-off-by: Michael S. Tsirkin --- changes from v2: add more comments changes from v1: add a comment target-arm/cpu64.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c index 04ce879..60acd24 100644 --- a/target-arm/cpu64.c +++ b/target-arm/cpu64.c @@ -58,6 +58,7 @@ static const ARMCPUInfo aarch64_cpus[] =3D { #ifdef CONFIG_USER_ONLY { .name =3D "any", .initfn =3D aarch64_any_initfn }, #endif + { .name =3D NULL } /* TODO: drop when we support more CPUs */ }; =20 static void aarch64_cpu_initfn(Object *obj) @@ -100,6 +101,11 @@ static void aarch64_cpu_register(const ARMCPUInfo *i= nfo) .class_init =3D info->class_init, }; =20 + /* TODO: drop when we support more CPUs - all entries will have name= set */ + if (!info->name) { + return; + } + type_info.name =3D g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); type_register(&type_info); g_free((void *)type_info.name); --=20 MST