From mboxrd@z Thu Jan 1 00:00:00 1970 From: moinejf@free.fr (Jean-Francois Moine) Date: Sun, 12 Jan 2014 14:20:00 +0100 Subject: [PATCH v2 20/28] drm/i2c: tda998x: move the TBG_CNTRL_0 register setting In-Reply-To: <20140112123159.GS15937@n2100.arm.linux.org.uk> References: <20140109120607.6a33bee5@armhf> <20140111183648.GH15937@n2100.arm.linux.org.uk> <20140112132321.757f3fa7@armhf> <20140112123159.GS15937@n2100.arm.linux.org.uk> Message-ID: <20140112142000.1f3e5ab5@armhf> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Sun, 12 Jan 2014 12:31:59 +0000 Russell King - ARM Linux wrote: > > So, in my patch 9, I was writing the REG_TBG_CNTRL_1 after writing > > REG_TBG_CNTRL_0, and you refused it. Here, I write REG_TBG_CNTRL_0 > > after the write of REG_TBG_CNTRL_1 in the HDMI sequence, and you still > > don't agree. > > > > What is the right way? > > No, both NAKS are for the exact same issue. > > Patch 9 inserted the write to REG_TBG_CNTRL_1 after REG_TBG_CNTRL_0. > Then in this patch you move REG_TBG_CNTRL_0 after all writes. > > Had you appropriately placed the write to REG_TBG_CNTRL_1 in patch 9 > in the first place, _this_ patch (patch 20) would not be required to > then move REG_TBG_CNTRL_0 after it. So, fixing patch 9 removes the > need for patch 20. Fixing the patch 9 gives: /* * Always generate sync polarity relative to input sync and * revert input stage toggled sync at output stage */ reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN; if (adj_mode->flags & DRM_MODE_FLAG_NHSYNC) reg |= TBG_CNTRL_1_H_TGL; if (adj_mode->flags & DRM_MODE_FLAG_NVSYNC) reg |= TBG_CNTRL_1_V_TGL; reg_write(priv, REG_TBG_CNTRL_1, reg); /* must be last register set: */ reg_clear(priv, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_ONCE); /* Only setup the info frames if the sink is HDMI */ if (priv->is_hdmi_sink) { /* We need to turn HDMI HDCP stuff on to get audio through */ reg &= ~TBG_CNTRL_1_DWIN_DIS; reg_write(priv, REG_TBG_CNTRL_1, reg); reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1)); reg_set(priv, REG_TX33, TX33_HDMI); tda998x_write_avi(priv, adj_mode); if (priv->params.audio_cfg) tda998x_configure_audio(priv, adj_mode, &priv->params); } and REG_TBG_CNTRL_1 is set in the HDMI branch (with REG_ENC_CNTRL and REG_TX33). Is this OK? -- Ken ar c'henta? | ** Breizh ha Linux atav! ** Jef | http://moinejf.free.fr/ From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jean-Francois Moine Subject: Re: [PATCH v2 20/28] drm/i2c: tda998x: move the TBG_CNTRL_0 register setting Date: Sun, 12 Jan 2014 14:20:00 +0100 Message-ID: <20140112142000.1f3e5ab5@armhf> References: <20140109120607.6a33bee5@armhf> <20140111183648.GH15937@n2100.arm.linux.org.uk> <20140112132321.757f3fa7@armhf> <20140112123159.GS15937@n2100.arm.linux.org.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from smtp3-g21.free.fr (smtp3-g21.free.fr [212.27.42.3]) by gabe.freedesktop.org (Postfix) with ESMTP id 1D70BFAE79 for ; Sun, 12 Jan 2014 05:20:39 -0800 (PST) In-Reply-To: <20140112123159.GS15937@n2100.arm.linux.org.uk> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: dri-devel-bounces@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org To: Russell King - ARM Linux Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org T24gU3VuLCAxMiBKYW4gMjAxNCAxMjozMTo1OSArMDAwMApSdXNzZWxsIEtpbmcgLSBBUk0gTGlu dXggPGxpbnV4QGFybS5saW51eC5vcmcudWs+IHdyb3RlOgoKPiA+IFNvLCBpbiBteSBwYXRjaCA5 LCBJIHdhcyB3cml0aW5nIHRoZSBSRUdfVEJHX0NOVFJMXzEgYWZ0ZXIgd3JpdGluZwo+ID4gUkVH X1RCR19DTlRSTF8wLCBhbmQgeW91IHJlZnVzZWQgaXQuIEhlcmUsIEkgd3JpdGUgUkVHX1RCR19D TlRSTF8wCj4gPiBhZnRlciB0aGUgd3JpdGUgb2YgUkVHX1RCR19DTlRSTF8xIGluIHRoZSBIRE1J IHNlcXVlbmNlLCBhbmQgeW91IHN0aWxsCj4gPiBkb24ndCBhZ3JlZS4KPiA+IAo+ID4gV2hhdCBp cyB0aGUgcmlnaHQgd2F5PyAgCj4gCj4gTm8sIGJvdGggTkFLUyBhcmUgZm9yIHRoZSBleGFjdCBz YW1lIGlzc3VlLgo+IAo+IFBhdGNoIDkgaW5zZXJ0ZWQgdGhlIHdyaXRlIHRvIFJFR19UQkdfQ05U UkxfMSBhZnRlciBSRUdfVEJHX0NOVFJMXzAuCj4gVGhlbiBpbiB0aGlzIHBhdGNoIHlvdSBtb3Zl IFJFR19UQkdfQ05UUkxfMCBhZnRlciBhbGwgd3JpdGVzLgo+IAo+IEhhZCB5b3UgYXBwcm9wcmlh dGVseSBwbGFjZWQgdGhlIHdyaXRlIHRvIFJFR19UQkdfQ05UUkxfMSBpbiBwYXRjaCA5Cj4gaW4g dGhlIGZpcnN0IHBsYWNlLCBfdGhpc18gcGF0Y2ggKHBhdGNoIDIwKSB3b3VsZCBub3QgYmUgcmVx dWlyZWQgdG8KPiB0aGVuIG1vdmUgUkVHX1RCR19DTlRSTF8wIGFmdGVyIGl0LiAgU28sIGZpeGlu ZyBwYXRjaCA5IHJlbW92ZXMgdGhlCj4gbmVlZCBmb3IgcGF0Y2ggMjAuCgpGaXhpbmcgdGhlIHBh dGNoIDkgZ2l2ZXM6CgoJLyoKCSAqIEFsd2F5cyBnZW5lcmF0ZSBzeW5jIHBvbGFyaXR5IHJlbGF0 aXZlIHRvIGlucHV0IHN5bmMgYW5kCgkgKiByZXZlcnQgaW5wdXQgc3RhZ2UgdG9nZ2xlZCBzeW5j IGF0IG91dHB1dCBzdGFnZQoJICovCglyZWcgPSBUQkdfQ05UUkxfMV9EV0lOX0RJUyB8IFRCR19D TlRSTF8xX1RHTF9FTjsKCWlmIChhZGpfbW9kZS0+ZmxhZ3MgJiBEUk1fTU9ERV9GTEFHX05IU1lO QykKCQlyZWcgfD0gVEJHX0NOVFJMXzFfSF9UR0w7CglpZiAoYWRqX21vZGUtPmZsYWdzICYgRFJN X01PREVfRkxBR19OVlNZTkMpCgkJcmVnIHw9IFRCR19DTlRSTF8xX1ZfVEdMOwoJcmVnX3dyaXRl KHByaXYsIFJFR19UQkdfQ05UUkxfMSwgcmVnKTsKCgkvKiBtdXN0IGJlIGxhc3QgcmVnaXN0ZXIg c2V0OiAqLwoJcmVnX2NsZWFyKHByaXYsIFJFR19UQkdfQ05UUkxfMCwgVEJHX0NOVFJMXzBfU1lO Q19PTkNFKTsKCgkvKiBPbmx5IHNldHVwIHRoZSBpbmZvIGZyYW1lcyBpZiB0aGUgc2luayBpcyBI RE1JICovCglpZiAocHJpdi0+aXNfaGRtaV9zaW5rKSB7CgkJLyogV2UgbmVlZCB0byB0dXJuIEhE TUkgSERDUCBzdHVmZiBvbiB0byBnZXQgYXVkaW8gdGhyb3VnaCAqLwoJCXJlZyAmPSB+VEJHX0NO VFJMXzFfRFdJTl9ESVM7CgkJcmVnX3dyaXRlKHByaXYsIFJFR19UQkdfQ05UUkxfMSwgcmVnKTsK CQlyZWdfd3JpdGUocHJpdiwgUkVHX0VOQ19DTlRSTCwgRU5DX0NOVFJMX0NUTF9DT0RFKDEpKTsK CQlyZWdfc2V0KHByaXYsIFJFR19UWDMzLCBUWDMzX0hETUkpOwoKCQl0ZGE5OTh4X3dyaXRlX2F2 aShwcml2LCBhZGpfbW9kZSk7CgoJCWlmIChwcml2LT5wYXJhbXMuYXVkaW9fY2ZnKQoJCQl0ZGE5 OTh4X2NvbmZpZ3VyZV9hdWRpbyhwcml2LCBhZGpfbW9kZSwgJnByaXYtPnBhcmFtcyk7Cgl9Cgph bmQgUkVHX1RCR19DTlRSTF8xIGlzIHNldCBpbiB0aGUgSERNSSBicmFuY2ggKHdpdGggUkVHX0VO Q19DTlRSTCBhbmQKUkVHX1RYMzMpLgoKSXMgdGhpcyBPSz8KCi0tIApLZW4gYXIgYydoZW50YcOx CXwJICAgICAgKiogQnJlaXpoIGhhIExpbnV4IGF0YXYhICoqCkplZgkJfAkJaHR0cDovL21vaW5l amYuZnJlZS5mci8KX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X18KZHJpLWRldmVsIG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3Jn Cmh0dHA6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2ZWwK From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751051AbaALNUo (ORCPT ); Sun, 12 Jan 2014 08:20:44 -0500 Received: from smtp3-g21.free.fr ([212.27.42.3]:54183 "EHLO smtp3-g21.free.fr" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750876AbaALNUl convert rfc822-to-8bit (ORCPT ); Sun, 12 Jan 2014 08:20:41 -0500 Date: Sun, 12 Jan 2014 14:20:00 +0100 From: Jean-Francois Moine To: Russell King - ARM Linux Cc: dri-devel@lists.freedesktop.org, Rob Clark , Dave Airlie , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 20/28] drm/i2c: tda998x: move the TBG_CNTRL_0 register setting Message-ID: <20140112142000.1f3e5ab5@armhf> In-Reply-To: <20140112123159.GS15937@n2100.arm.linux.org.uk> References: <20140109120607.6a33bee5@armhf> <20140111183648.GH15937@n2100.arm.linux.org.uk> <20140112132321.757f3fa7@armhf> <20140112123159.GS15937@n2100.arm.linux.org.uk> X-Mailer: Claws Mail 3.9.3 (GTK+ 2.24.22; arm-unknown-linux-gnueabihf) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, 12 Jan 2014 12:31:59 +0000 Russell King - ARM Linux wrote: > > So, in my patch 9, I was writing the REG_TBG_CNTRL_1 after writing > > REG_TBG_CNTRL_0, and you refused it. Here, I write REG_TBG_CNTRL_0 > > after the write of REG_TBG_CNTRL_1 in the HDMI sequence, and you still > > don't agree. > > > > What is the right way? > > No, both NAKS are for the exact same issue. > > Patch 9 inserted the write to REG_TBG_CNTRL_1 after REG_TBG_CNTRL_0. > Then in this patch you move REG_TBG_CNTRL_0 after all writes. > > Had you appropriately placed the write to REG_TBG_CNTRL_1 in patch 9 > in the first place, _this_ patch (patch 20) would not be required to > then move REG_TBG_CNTRL_0 after it. So, fixing patch 9 removes the > need for patch 20. Fixing the patch 9 gives: /* * Always generate sync polarity relative to input sync and * revert input stage toggled sync at output stage */ reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN; if (adj_mode->flags & DRM_MODE_FLAG_NHSYNC) reg |= TBG_CNTRL_1_H_TGL; if (adj_mode->flags & DRM_MODE_FLAG_NVSYNC) reg |= TBG_CNTRL_1_V_TGL; reg_write(priv, REG_TBG_CNTRL_1, reg); /* must be last register set: */ reg_clear(priv, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_ONCE); /* Only setup the info frames if the sink is HDMI */ if (priv->is_hdmi_sink) { /* We need to turn HDMI HDCP stuff on to get audio through */ reg &= ~TBG_CNTRL_1_DWIN_DIS; reg_write(priv, REG_TBG_CNTRL_1, reg); reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1)); reg_set(priv, REG_TX33, TX33_HDMI); tda998x_write_avi(priv, adj_mode); if (priv->params.audio_cfg) tda998x_configure_audio(priv, adj_mode, &priv->params); } and REG_TBG_CNTRL_1 is set in the HDMI branch (with REG_ENC_CNTRL and REG_TX33). Is this OK? -- Ken ar c'hentañ | ** Breizh ha Linux atav! ** Jef | http://moinejf.free.fr/