Re: [Qemu-devel] [PATCH v2 7/7] add support for hyper-v timers http://msdn.microsoft.com/en-us/library/windows/hardware/ff541625%28v=vs.85%29.aspx This code is generic for activating reference time counter or virtual reference time stamp counter

[Marcelo Tosatti <mtosatti@redhat.com>]

Subject for 7/7 contains commit log, otherwise

Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com>

On Fri, Jan 24, 2014 at 12:40:49AM +1100, Vadim Rozenfeld wrote:
> Signed-off-by: Vadim Rozenfeld <vrozenfe@redhat.com>
> ---
>  linux-headers/asm-x86/hyperv.h |  3 +++
>  linux-headers/linux/kvm.h      |  1 +
>  target-i386/cpu-qom.h          |  1 +
>  target-i386/cpu.c              |  1 +
>  target-i386/cpu.h              |  1 +
>  target-i386/kvm.c              | 21 ++++++++++++++++++++-
>  target-i386/machine.c          | 21 +++++++++++++++++++++
>  7 files changed, 48 insertions(+), 1 deletion(-)
> 
> diff --git a/linux-headers/asm-x86/hyperv.h b/linux-headers/asm-x86/hyperv.h
> index b8f1c01..3b400ee 100644
> --- a/linux-headers/asm-x86/hyperv.h
> +++ b/linux-headers/asm-x86/hyperv.h
> @@ -149,6 +149,9 @@
>  /* MSR used to read the per-partition time reference counter */
>  #define HV_X64_MSR_TIME_REF_COUNT		0x40000020
>  
> +/* A partition's reference time stamp counter (TSC) page */
> +#define HV_X64_MSR_REFERENCE_TSC		0x40000021
> +
>  /* MSR used to retrieve the TSC frequency */
>  #define HV_X64_MSR_TSC_FREQUENCY		0x40000022
>  
> diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
> index 5a49671..999fb13 100644
> --- a/linux-headers/linux/kvm.h
> +++ b/linux-headers/linux/kvm.h
> @@ -674,6 +674,7 @@ struct kvm_ppc_smmu_info {
>  #define KVM_CAP_ARM_EL1_32BIT 93
>  #define KVM_CAP_SPAPR_MULTITCE 94
>  #define KVM_CAP_EXT_EMUL_CPUID 95
> +#define KVM_CAP_HYPERV_TIME 96
>  
>  #ifdef KVM_CAP_IRQ_ROUTING
>  
> diff --git a/target-i386/cpu-qom.h b/target-i386/cpu-qom.h
> index d1751a4..722f11a 100644
> --- a/target-i386/cpu-qom.h
> +++ b/target-i386/cpu-qom.h
> @@ -69,6 +69,7 @@ typedef struct X86CPU {
>      bool hyperv_vapic;
>      bool hyperv_relaxed_timing;
>      int hyperv_spinlock_attempts;
> +    bool hyperv_time;
>      bool check_cpuid;
>      bool enforce_cpuid;
>  
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index 0eea8c7..ff3290c 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -2744,6 +2744,7 @@ static Property x86_cpu_properties[] = {
>      { .name  = "hv-spinlocks", .info  = &qdev_prop_spinlocks },
>      DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
>      DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
> +    DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
>      DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false),
>      DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
>      DEFINE_PROP_END_OF_LIST()
> diff --git a/target-i386/cpu.h b/target-i386/cpu.h
> index d75a793..73174a3 100644
> --- a/target-i386/cpu.h
> +++ b/target-i386/cpu.h
> @@ -849,6 +849,7 @@ typedef struct CPUX86State {
>      uint64_t msr_hv_hypercall;
>      uint64_t msr_hv_guest_os_id;
>      uint64_t msr_hv_vapic;
> +    uint64_t msr_hv_tsc;
>  
>      /* exception/interrupt handling */
>      int error_code;
> diff --git a/target-i386/kvm.c b/target-i386/kvm.c
> index 6563dcb..135d369 100644
> --- a/target-i386/kvm.c
> +++ b/target-i386/kvm.c
> @@ -73,6 +73,7 @@ static bool has_msr_kvm_steal_time;
>  static int lm_capable_kernel;
>  static bool has_msr_hv_hypercall;
>  static bool has_msr_hv_vapic;
> +static bool has_msr_hv_tsc;
>  
>  static bool has_msr_architectural_pmu;
>  static uint32_t num_architectural_pmu_counters;
> @@ -439,6 +440,7 @@ static bool hyperv_hypercall_available(X86CPU *cpu)
>  static bool hyperv_enabled(X86CPU *cpu)
>  {
>      return hyperv_hypercall_available(cpu) ||
> +           cpu->hyperv_time  ||
>             cpu->hyperv_relaxed_timing;
>  }
>  
> @@ -493,7 +495,13 @@ int kvm_arch_init_vcpu(CPUState *cs)
>              c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
>              has_msr_hv_vapic = true;
>          }
> -
> +        if (cpu->hyperv_time &&
> +            kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
> +            c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
> +            c->eax |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
> +            c->eax |= 0x200;
> +            has_msr_hv_tsc = true;
> +        }
>          c = &cpuid_data.entries[cpuid_i++];
>          c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
>          if (cpu->hyperv_relaxed_timing) {
> @@ -1191,6 +1199,11 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
>              kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE,
>                                env->msr_hv_vapic);
>          }
> +        if (has_msr_hv_tsc) {
> +            kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_REFERENCE_TSC,
> +                              env->msr_hv_tsc);
> +        }
> +
>          if (has_msr_feature_control) {
>              kvm_msr_entry_set(&msrs[n++], MSR_IA32_FEATURE_CONTROL,
>                                env->msr_ia32_feature_control);
> @@ -1476,6 +1489,9 @@ static int kvm_get_msrs(X86CPU *cpu)
>      if (has_msr_hv_vapic) {
>          msrs[n++].index = HV_X64_MSR_APIC_ASSIST_PAGE;
>      }
> +    if (has_msr_hv_tsc) {
> +        msrs[n++].index = HV_X64_MSR_REFERENCE_TSC;
> +    }
>  
>      msr_data.info.nmsrs = n;
>      ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
> @@ -1590,6 +1606,9 @@ static int kvm_get_msrs(X86CPU *cpu)
>          case HV_X64_MSR_APIC_ASSIST_PAGE:
>              env->msr_hv_vapic = msrs[i].data;
>              break;
> +        case HV_X64_MSR_REFERENCE_TSC:
> +            env->msr_hv_tsc = msrs[i].data;
> +            break;
>          }
>      }
>  
> diff --git a/target-i386/machine.c b/target-i386/machine.c
> index 8fc81bc..07cc87b 100644
> --- a/target-i386/machine.c
> +++ b/target-i386/machine.c
> @@ -545,6 +545,24 @@ static const VMStateDescription vmstate_msr_hyperv_vapic = {
>      }
>  };
>  
> +static bool hyperv_time_enable_needed(void *opaque)
> +{
> +    X86CPU *cpu = opaque;
> +    CPUX86State *env = &cpu->env;
> +
> +    return env->msr_hv_tsc != 0;
> +}
> +
> +static const VMStateDescription vmstate_msr_hyperv_time = {
> +    .name = "cpu/msr_hyperv_time",
> +    .version_id = 1,
> +    .minimum_version_id = 1,
> +    .minimum_version_id_old = 1,
> +    .fields      = (VMStateField []) {
> +        VMSTATE_UINT64(env.msr_hv_tsc, X86CPU),
> +        VMSTATE_END_OF_LIST()
> +    }
> +};
>  const VMStateDescription vmstate_x86_cpu = {
>      .name = "cpu",
>      .version_id = 12,
> @@ -682,6 +700,9 @@ const VMStateDescription vmstate_x86_cpu = {
>          }, {
>              .vmsd = &vmstate_msr_hyperv_vapic,
>              .needed = hyperv_vapic_enable_needed,
> +        }, {
> +            .vmsd = &vmstate_msr_hyperv_time,
> +            .needed = hyperv_time_enable_needed,
>          } , {
>              /* empty */
>          }
> -- 
> 1.8.1.4