Re: [RFC][PATCH 5/5] arch: Sanitize atomic_t bitwise ops

[Peter Zijlstra <peterz@infradead.org>]

On Thu, Feb 06, 2014 at 03:43:19PM +0100, Geert Uytterhoeven wrote:
> On Thu, Feb 6, 2014 at 2:48 PM, Peter Zijlstra <peterz@infradead.org> wrote:
> > --- a/arch/m68k/include/asm/atomic.h
> > +++ b/arch/m68k/include/asm/atomic.h
> > @@ -76,6 +76,9 @@ static inline int atomic_##op##_return(i
> >
> >  ATOMIC_OP(add, +=)
> >  ATOMIC_OP(sub, -=)
> > +ATOMIC_OP(and, &=)
> > +ATOMIC_OP(or , |=)
> > +ATOMIC_OP(xor, ^=)
> 
> This last one ain't gonna fly. Given
> 
> static inline void atomic_##op(int i, atomic_t *v)                     \
> {                                                                      \
>        __asm__ __volatile__(#op "l %1,%0" : "+m" (*v) : ASM_DI (i));   \
> }
> 
> from the previous patch, it'll generate the "xorl" mnemonic, which
> IIRC does not exist. It's called "eorl".

Some instruction sets I googled, others I didn't; guess what I did (or
rather didn't do) for m68k :-)

ok I'll make that:

#define ATOMIC_OP(op, aop, cop)

ATOMIC_OP(xor, eor, ^=)

I had to so similar things on a few other archs as well, asm instruction
names are odd sometimes.

Thanks!