From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH 2/2] drm/i915: PSR HSW: update after
	enabling sprite.
Date: Fri, 7 Feb 2014 21:17:45 +0200
Message-ID: <20140207191745.GC3891@intel.com>
References: <1391796588-2015-1-git-send-email-rodrigo.vivi@gmail.com>
	<1391796588-2015-2-git-send-email-rodrigo.vivi@gmail.com>
Mime-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Return-path: <intel-gfx-bounces@lists.freedesktop.org>
Received: from mga09.intel.com (mga09.intel.com [134.134.136.24])
	by gabe.freedesktop.org (Postfix) with ESMTP id 812FAFBC8F
	for <intel-gfx@lists.freedesktop.org>;
	Fri,  7 Feb 2014 11:17:50 -0800 (PST)
Content-Disposition: inline
In-Reply-To: <1391796588-2015-2-git-send-email-rodrigo.vivi@gmail.com>
List-Unsubscribe: <http://lists.freedesktop.org/mailman/options/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <http://lists.freedesktop.org/archives/intel-gfx>
List-Post: <mailto:intel-gfx@lists.freedesktop.org>
List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help>
List-Subscribe: <http://lists.freedesktop.org/mailman/listinfo/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe>
Sender: intel-gfx-bounces@lists.freedesktop.org
Errors-To: intel-gfx-bounces@lists.freedesktop.org
To: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Cc: intel-gfx@lists.freedesktop.org
List-Id: intel-gfx@lists.freedesktop.org

On Fri, Feb 07, 2014 at 04:09:48PM -0200, Rodrigo Vivi wrote:
> On the current structure HSW doesn't support PSR with sprites enabled
> but sprites can be enabled after PSR was enabled what would cause
> user to miss screen updates.
> =

> Cc: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
> ---
>  drivers/gpu/drm/i915/intel_sprite.c | 2 ++
>  1 file changed, 2 insertions(+)
> =

> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/i=
ntel_sprite.c
> index 336ae6c..3132686 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -318,6 +318,8 @@ ivb_update_plane(struct drm_plane *plane, struct drm_=
crtc *crtc,
>  	I915_WRITE(SPRSURF(pipe),
>  		   i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
>  	POSTING_READ(SPRSURF(pipe));
> +
> +	intel_edp_psr_update(dev);

I was thinking this might be better placed in intel_update_plane()
since the fbc/ips stuff is there, but I can live with it being here too.

But should if have a HSW check on it? BDW doesn't have this restriction
anymore, right?

>  }
>  =

>  static void
> -- =

> 1.7.11.7

-- =

Ville Syrj=E4l=E4
Intel OTC