From mboxrd@z Thu Jan 1 00:00:00 1970 From: andrew@lunn.ch (Andrew Lunn) Date: Mon, 10 Feb 2014 18:53:50 +0100 Subject: [PATCH 6/6] dt: Update binding information for mvebu gating clocks with Armada 380/385 In-Reply-To: <1392053569-28037-7-git-send-email-gregory.clement@free-electrons.com> References: <1392053569-28037-1-git-send-email-gregory.clement@free-electrons.com> <1392053569-28037-7-git-send-email-gregory.clement@free-electrons.com> Message-ID: <20140210175350.GD9995@lunn.ch> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org > +The following is a list of provided IDs for Armada 380/385: > +ID Clock Peripheral > +----------------------------------- > +0 audio Audio > +2 ge2 Gigabit Ethernet 2 > +3 ge1 Gigabit Ethernet 1 > +4 ge0 Gigabit Ethernet 0 > +5 pex1 PCIe 1 > +6 pex2 PCIe 2 > +7 pex3 PCIe 3 > +8 pex4 PCIe 0 Is that last one a typo? It at least looks a bit odd. Thanks Andrew From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Lunn Subject: Re: [PATCH 6/6] dt: Update binding information for mvebu gating clocks with Armada 380/385 Date: Mon, 10 Feb 2014 18:53:50 +0100 Message-ID: <20140210175350.GD9995@lunn.ch> References: <1392053569-28037-1-git-send-email-gregory.clement@free-electrons.com> <1392053569-28037-7-git-send-email-gregory.clement@free-electrons.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <1392053569-28037-7-git-send-email-gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Gregory CLEMENT Cc: Mike Turquette , Thomas Petazzoni , Lior Amsalem , Tawfik Bayouk , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Nadav Haklai , Ezequiel Garcia , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Sebastian Hesselbarth List-Id: devicetree@vger.kernel.org > +The following is a list of provided IDs for Armada 380/385: > +ID Clock Peripheral > +----------------------------------- > +0 audio Audio > +2 ge2 Gigabit Ethernet 2 > +3 ge1 Gigabit Ethernet 1 > +4 ge0 Gigabit Ethernet 0 > +5 pex1 PCIe 1 > +6 pex2 PCIe 2 > +7 pex3 PCIe 3 > +8 pex4 PCIe 0 Is that last one a typo? It at least looks a bit odd. Thanks Andrew -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753034AbaBJRyS (ORCPT ); Mon, 10 Feb 2014 12:54:18 -0500 Received: from vps0.lunn.ch ([178.209.37.122]:54198 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752837AbaBJRyQ (ORCPT ); Mon, 10 Feb 2014 12:54:16 -0500 Date: Mon, 10 Feb 2014 18:53:50 +0100 From: Andrew Lunn To: Gregory CLEMENT Cc: Mike Turquette , Thomas Petazzoni , Lior Amsalem , Tawfik Bayouk , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Nadav Haklai , Ezequiel Garcia , linux-arm-kernel@lists.infradead.org, Sebastian Hesselbarth Subject: Re: [PATCH 6/6] dt: Update binding information for mvebu gating clocks with Armada 380/385 Message-ID: <20140210175350.GD9995@lunn.ch> References: <1392053569-28037-1-git-send-email-gregory.clement@free-electrons.com> <1392053569-28037-7-git-send-email-gregory.clement@free-electrons.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1392053569-28037-7-git-send-email-gregory.clement@free-electrons.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > +The following is a list of provided IDs for Armada 380/385: > +ID Clock Peripheral > +----------------------------------- > +0 audio Audio > +2 ge2 Gigabit Ethernet 2 > +3 ge1 Gigabit Ethernet 1 > +4 ge0 Gigabit Ethernet 0 > +5 pex1 PCIe 1 > +6 pex2 PCIe 2 > +7 pex3 PCIe 3 > +8 pex4 PCIe 0 Is that last one a typo? It at least looks a bit odd. Thanks Andrew