From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH v3 2/2] drm/i915: Prevent MI_DISPLAY_FLIP
 straddling two cachelines on IVB
Date: Tue, 11 Feb 2014 22:34:48 +0200
Message-ID: <20140211203448.GX3891@intel.com>
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To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org, Enrico Tagliavini <enrico.tagliavini@gmail.com>, Bjoern C <lkml@call-home.ch>, Alexandru DAMIAN <alexandru.damian@intel.com>
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On Tue, Feb 11, 2014 at 08:19:13PM +0000, Chris Wilson wrote:
> On Tue, Feb 11, 2014 at 07:52:06PM +0200, ville.syrjala@linux.intel.com w=
rote:
> > From: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> > =

> > According to BSpec the entire MI_DISPLAY_FLIP packet must be contained
> > in a single cacheline. Make sure that happens.
> > =

> > v2: Use intel_ring_begin_cacheline_safe()
> > v3: Use intel_ring_cacheline_align() (Chris)
> > =

> > Cc: Bjoern C <lkml@call-home.ch>
> > Cc: Alexandru DAMIAN <alexandru.damian@intel.com>
> > Cc: Enrico Tagliavini <enrico.tagliavini@gmail.com>
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=3D74053
> > Signed-off-by: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> =

> I would have used intel_ring_align_cacheline() as it seems more natural
> for me to say...

I had it as intel_ring_align_to_cacheline(), but then changed it when I
saw Daniel's suggestion for the name. So you can blame Daniel for this ;)
But I have no emotional attachment to the chosen name. So if you prefer
we rename it, I'm fine with that.

-- =

Ville Syrj=E4l=E4
Intel OTC