From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Avoid div by zero when pixel clock is large
Date: Fri, 14 Feb 2014 14:40:39 +0200 [thread overview]
Message-ID: <20140214124039.GI3852@intel.com> (raw)
In-Reply-To: <20140214122829.GF32602@nuc-i3427.alporthouse.com>
On Fri, Feb 14, 2014 at 12:28:29PM +0000, Chris Wilson wrote:
> On Fri, Feb 14, 2014 at 02:18:57PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Make sure the line_time_us isn't zero in the gmch watermarks code as
> > that would cause a div by zero. This can be triggered by specifying
> > a very fast pixel clock for the mode.
>
> Very fast but valid?
74.25 GHz. I'm not sure which way you would classify that :)
> If it was just very fast, we should have rejected
> the mode line.
Except we do more or less zero checks on the mode supplied to the
setcrtc ioctl. Something we should really get fixed at some point.
--
Ville Syrjälä
Intel OTC
next prev parent reply other threads:[~2014-02-14 12:40 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-02-14 12:18 [PATCH] drm/i915: Avoid div by zero when pixel clock is large ville.syrjala
2014-02-14 12:28 ` Chris Wilson
2014-02-14 12:40 ` Ville Syrjälä [this message]
2014-03-06 20:57 ` Daniel Vetter
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