From: Beniamino Galvani <b.galvani@gmail.com>
To: Li Guang <lig.fnst@cn.fujitsu.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
Peter Crosthwaite <peter.crosthwaite@xilinx.com>,
qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 1/7] allwinner-a10-pic: set vector address when an interrupt is pending
Date: Wed, 19 Feb 2014 00:17:38 +0100 [thread overview]
Message-ID: <20140218231737.GA24042@gmail.com> (raw)
In-Reply-To: <5302D30F.6000503@cn.fujitsu.com>
On Tue, Feb 18, 2014 at 11:27:11AM +0800, Li Guang wrote:
> Hi,
>
> Beniamino Galvani wrote:
> >This patch implements proper updating of the vector register which
> >should hold, according to the A10 user manual, the vector address for
> >the interrupt currently active on the CPU IRQ input.
> >
> >Interrupt priority is not implemented at the moment and thus the first
> >pending interrupt is returned.
> >
> >Signed-off-by: Beniamino Galvani<b.galvani@gmail.com>
> >---
> > hw/intc/allwinner-a10-pic.c | 11 ++++++++++-
> > 1 file changed, 10 insertions(+), 1 deletion(-)
> >
> >diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c
> >index 407d563..bb2351f 100644
> >--- a/hw/intc/allwinner-a10-pic.c
> >+++ b/hw/intc/allwinner-a10-pic.c
> >@@ -23,11 +23,20 @@
> > static void aw_a10_pic_update(AwA10PICState *s)
> > {
> > uint8_t i;
> >- int irq = 0, fiq = 0;
> >+ int irq = 0, fiq = 0, pending;
> >+
> >+ s->vector = 0;
> >
> > for (i = 0; i< AW_A10_PIC_REG_NUM; i++) {
> > irq |= s->irq_pending[i]& ~s->mask[i];
> > fiq |= s->select[i]& s->irq_pending[i]& ~s->mask[i];
> >+
> >+ if (!s->vector) {
> >+ pending = ffs(s->irq_pending[i]& ~s->mask[i]);
> >+ if (pending) {
> >+ s->vector = (i * 32 + pending - 1) * 4;
>
> this maybe should determined also by interrupt priority,
We can add interrupt priority logic later if it's needed, but at the
moment I don't think it's used by Linux.
> and you should also remove s->vector assignment at register write phase.
You're right, the register is read-only; I will remove it from the
write function.
Beniamino
next prev parent reply other threads:[~2014-02-18 23:18 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-02-17 17:43 [Qemu-devel] [PATCH 0/7] Allwinner A10 fixes Beniamino Galvani
2014-02-17 17:43 ` [Qemu-devel] [PATCH 1/7] allwinner-a10-pic: set vector address when an interrupt is pending Beniamino Galvani
2014-02-18 3:27 ` Li Guang
2014-02-18 23:17 ` Beniamino Galvani [this message]
2014-02-17 17:43 ` [Qemu-devel] [PATCH 2/7] allwinner-a10-pic: fix interrupt clear behaviour Beniamino Galvani
2014-02-18 3:49 ` Li Guang
2014-02-18 23:22 ` Beniamino Galvani
2014-02-19 2:02 ` Li Guang
2014-02-22 14:20 ` Beniamino Galvani
2014-02-24 6:45 ` Li Guang
2014-02-24 22:50 ` Beniamino Galvani
2014-02-25 1:08 ` Li Guang
2014-02-17 17:43 ` [Qemu-devel] [PATCH 3/7] allwinner-a10-pit: avoid generation of spurious interrupts Beniamino Galvani
2014-02-18 4:17 ` Li Guang
2014-02-18 23:26 ` Beniamino Galvani
2014-02-19 1:58 ` Li Guang
2014-02-17 17:43 ` [Qemu-devel] [PATCH 4/7] allwinner-a10-pit: use level triggered interrupts Beniamino Galvani
2014-02-18 3:51 ` Li Guang
2014-02-18 23:29 ` Beniamino Galvani
2014-02-17 17:43 ` [Qemu-devel] [PATCH 5/7] allwinner-a10-pit: implement prescaler and source selection Beniamino Galvani
2014-02-17 17:43 ` [Qemu-devel] [PATCH 6/7] allwinner-emac: set autonegotiation complete bit on link up Beniamino Galvani
2014-02-17 17:43 ` [Qemu-devel] [PATCH 7/7] allwinner-emac: update irq status after writes to interrupt registers Beniamino Galvani
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