From mboxrd@z Thu Jan 1 00:00:00 1970 From: Arnd Bergmann Subject: Re: [PATCH 7/7] PCI: designware: split samsung and fsl bindings Date: Fri, 28 Feb 2014 21:03:01 +0100 Message-ID: <201402282103.01897.arnd@arndb.de> References: <1393608523-17509-1-git-send-email-l.stach@pengutronix.de> <1393608523-17509-8-git-send-email-l.stach@pengutronix.de> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1393608523-17509-8-git-send-email-l.stach@pengutronix.de> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Lucas Stach Cc: Mark Rutland , devicetree@vger.kernel.org, Jingoo Han , linux-samsung-soc@vger.kernel.org, Richard Zhu , kernel@pengutronix.de, linux-sh@vger.kernel.org, Tim Harvey , Stephen Warren , Bjorn Helgaas , Simon Horman , Thierry Reding , Ben Dooks , linux-tegra@vger.kernel.org, Kukjin Kim , Shawn Guo , linux-arm-kernel@lists.infradead.org List-Id: linux-samsung-soc@vger.kernel.org On Friday 28 February 2014, Lucas Stach wrote: > +Required properties: > +- compatible: "fsl,imx6q-pcie" > +- reg: base addresse and length of the pcie controller > +- interrupts: First entry must contain interrupt handle for controller > + INTA output. I think this should be documented as "optional" and only for backwards compatibility with old kernels. > +- clocks: Must contain an entry for each entry in clock-names. > + See ../clocks/clock-bindings.txt for details. > +- clock-names: Must include the following entries: > + - "pcie_ref_125m" > + - "sata_ref_100m" > + - "lvds_gate" > + - "pcie_axi" I don't understand why you have completely different clocks here from the exynos documentation. The clock names should really be the same. Also, why do you have a "sata_ref_100m" clock? Is this just driving a device that happens to be on-board for a specific machine? Same for the "lvds_gate". Arnd From mboxrd@z Thu Jan 1 00:00:00 1970 From: Arnd Bergmann Date: Fri, 28 Feb 2014 20:03:01 +0000 Subject: Re: [PATCH 7/7] PCI: designware: split samsung and fsl bindings Message-Id: <201402282103.01897.arnd@arndb.de> List-Id: References: <1393608523-17509-1-git-send-email-l.stach@pengutronix.de> <1393608523-17509-8-git-send-email-l.stach@pengutronix.de> In-Reply-To: <1393608523-17509-8-git-send-email-l.stach@pengutronix.de> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: linux-arm-kernel@lists.infradead.org On Friday 28 February 2014, Lucas Stach wrote: > +Required properties: > +- compatible: "fsl,imx6q-pcie" > +- reg: base addresse and length of the pcie controller > +- interrupts: First entry must contain interrupt handle for controller > + INTA output. I think this should be documented as "optional" and only for backwards compatibility with old kernels. > +- clocks: Must contain an entry for each entry in clock-names. > + See ../clocks/clock-bindings.txt for details. > +- clock-names: Must include the following entries: > + - "pcie_ref_125m" > + - "sata_ref_100m" > + - "lvds_gate" > + - "pcie_axi" I don't understand why you have completely different clocks here from the exynos documentation. The clock names should really be the same. Also, why do you have a "sata_ref_100m" clock? Is this just driving a device that happens to be on-board for a specific machine? Same for the "lvds_gate". Arnd From mboxrd@z Thu Jan 1 00:00:00 1970 From: arnd@arndb.de (Arnd Bergmann) Date: Fri, 28 Feb 2014 21:03:01 +0100 Subject: [PATCH 7/7] PCI: designware: split samsung and fsl bindings In-Reply-To: <1393608523-17509-8-git-send-email-l.stach@pengutronix.de> References: <1393608523-17509-1-git-send-email-l.stach@pengutronix.de> <1393608523-17509-8-git-send-email-l.stach@pengutronix.de> Message-ID: <201402282103.01897.arnd@arndb.de> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Friday 28 February 2014, Lucas Stach wrote: > +Required properties: > +- compatible: "fsl,imx6q-pcie" > +- reg: base addresse and length of the pcie controller > +- interrupts: First entry must contain interrupt handle for controller > + INTA output. I think this should be documented as "optional" and only for backwards compatibility with old kernels. > +- clocks: Must contain an entry for each entry in clock-names. > + See ../clocks/clock-bindings.txt for details. > +- clock-names: Must include the following entries: > + - "pcie_ref_125m" > + - "sata_ref_100m" > + - "lvds_gate" > + - "pcie_axi" I don't understand why you have completely different clocks here from the exynos documentation. The clock names should really be the same. Also, why do you have a "sata_ref_100m" clock? Is this just driving a device that happens to be on-board for a specific machine? Same for the "lvds_gate". Arnd