Re: [Qemu-devel] [PATCH v2 1/7] allwinner-a10-pic: set vector address when an interrupt is pending

[Beniamino Galvani <b.galvani@gmail.com>]

On Mon, Mar 03, 2014 at 09:16:13PM +1000, Peter Crosthwaite wrote:
> On Mon, Mar 3, 2014 at 12:06 AM, Beniamino Galvani <b.galvani@gmail.com> wrote:
> > This patch implements proper updating of the vector register which
> > should hold, according to the A10 user manual, the vector address for
> > the interrupt currently active on the CPU IRQ input.
> >
> > Interrupt priority is not implemented at the moment and thus the first
> > pending interrupt is returned.
> >
> 
> With all these allwinner cores do we have docs for any of them? Ive
> seen contributor claims that both enet and intc are undocumented but I
> saw a passing reference to a document for the timer. Is there anything
> useful resembling register specs for any of these patches? (not that
> that stops us from contributing - it just makes accurate review
> easier!).
> 
> > Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
> 
> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
> 

AFAIK, this is the most complete datasheet available:

http://dl.linux-sunxi.org/A10/A10%20User%20Manual%20-%20v1.20%20%282012-04-09,%20DECRYPTED%29.pdf

Interrupt controller and timer are documented, EMAC is not.

Beniamino

> > ---
> >  hw/intc/allwinner-a10-pic.c |   14 ++++++++++----
> >  1 file changed, 10 insertions(+), 4 deletions(-)
> >
> > diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c
> > index 407d563..00f3c11 100644
> > --- a/hw/intc/allwinner-a10-pic.c
> > +++ b/hw/intc/allwinner-a10-pic.c
> > @@ -23,11 +23,20 @@
> >  static void aw_a10_pic_update(AwA10PICState *s)
> >  {
> >      uint8_t i;
> > -    int irq = 0, fiq = 0;
> > +    int irq = 0, fiq = 0, pending;
> > +
> > +    s->vector = 0;
> >
> >      for (i = 0; i < AW_A10_PIC_REG_NUM; i++) {
> >          irq |= s->irq_pending[i] & ~s->mask[i];
> >          fiq |= s->select[i] & s->irq_pending[i] & ~s->mask[i];
> > +
> > +        if (!s->vector) {
> > +            pending = ffs(s->irq_pending[i] & ~s->mask[i]);
> > +            if (pending) {
> > +                s->vector = (i * 32 + pending - 1) * 4;
> > +            }
> > +        }
> >      }
> >
> >      qemu_set_irq(s->parent_irq, !!irq);
> > @@ -84,9 +93,6 @@ static void aw_a10_pic_write(void *opaque, hwaddr offset, uint64_t value,
> >      uint8_t index = (offset & 0xc) / 4;
> >
> >      switch (offset) {
> > -    case AW_A10_PIC_VECTOR:
> > -        s->vector = value & ~0x3;
> > -        break;
> >      case AW_A10_PIC_BASE_ADDR:
> >          s->base_addr = value & ~0x3;
> >      case AW_A10_PIC_PROTECT:
> > --
> > 1.7.10.4
> >
> >