From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45400) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WLQH1-00070Z-A2 for qemu-devel@nongnu.org; Wed, 05 Mar 2014 23:51:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WLQGv-0002K9-BF for qemu-devel@nongnu.org; Wed, 05 Mar 2014 23:51:11 -0500 Date: Thu, 6 Mar 2014 15:51:01 +1100 From: Anton Blanchard Message-ID: <20140306155101.343be99b@kryten> In-Reply-To: <20140306154912.10ba5a99@kryten> References: <20140306154912.10ba5a99@kryten> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [PATCH 3/4] target-ppc: POWER7+ supports the MSR_VSX bit List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Without MSR_VSX we die early during a Linux boot. Signed-off-by: Anton Blanchard --- Index: b/target-ppc/translate_init.c =================================================================== --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -7117,7 +7117,7 @@ POWERPC_FAMILY(POWER7P)(ObjectClass *oc, PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206; - pcc->msr_mask = 0x800000000204FF37ULL; + pcc->msr_mask = 0x800000000284FF37ULL; pcc->mmu_model = POWERPC_MMU_2_06; #if defined(CONFIG_SOFTMMU) pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;