diff for duplicates of <20140309085357.GA4695@katana> diff --git a/a/1.txt b/N1/1.txt index 3869995..73e2d9a 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,11 +1,11 @@ On Fri, Mar 07, 2014 at 10:12:50PM +0800, Chew Chiau Ee wrote: -> From: Chew, Chiau Ee <chiau.ee.chew-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> +> From: Chew, Chiau Ee <chiau.ee.chew@intel.com> > > All the I2C controllers on Intel BayTrail LPSS subsystem able > to support 10-bit addressing mode functionality. > -> Signed-off-by: Chew, Chiau Ee <chiau.ee.chew-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> -> Signed-off-by: Ong, Boon Leong <boon.leong.ong-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> +> Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com> +> Signed-off-by: Ong, Boon Leong <boon.leong.ong@intel.com> > --- > drivers/i2c/busses/i2c-designware-pcidrv.c | 17 +++++++++++------ > 1 files changed, 11 insertions(+), 6 deletions(-) diff --git a/a/content_digest b/N1/content_digest index 59fe4ca..947501f 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,23 +1,22 @@ "ref\01394201571-11681-1-git-send-email-chiau.ee.chew@intel.com\0" "ref\01394201571-11681-2-git-send-email-chiau.ee.chew@intel.com\0" - "ref\01394201571-11681-2-git-send-email-chiau.ee.chew-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org\0" - "From\0Wolfram Sang <wsa-z923LK4zBo2bacvFa/9K2g@public.gmane.org>\0" + "From\0Wolfram Sang <wsa@the-dreams.de>\0" "Subject\0Re: [PATCH 1/2] i2c: designware-pci: add 10-bit addressing mode functionality for BYT I2C\0" "Date\0Sun, 9 Mar 2014 09:53:58 +0100\0" - "To\0Chew Chiau Ee <chiau.ee.chew-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>\0" - "Cc\0Mika Westerberg <mika.westerberg-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>" - linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - " linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" + "To\0Chew Chiau Ee <chiau.ee.chew@intel.com>\0" + "Cc\0Mika Westerberg <mika.westerberg@linux.intel.com>" + linux-i2c@vger.kernel.org + " linux-kernel@vger.kernel.org\0" "\01:1\0" "b\0" "On Fri, Mar 07, 2014 at 10:12:50PM +0800, Chew Chiau Ee wrote:\n" - "> From: Chew, Chiau Ee <chiau.ee.chew-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>\n" + "> From: Chew, Chiau Ee <chiau.ee.chew@intel.com>\n" "> \n" "> All the I2C controllers on Intel BayTrail LPSS subsystem able\n" "> to support 10-bit addressing mode functionality.\n" "> \n" - "> Signed-off-by: Chew, Chiau Ee <chiau.ee.chew-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>\n" - "> Signed-off-by: Ong, Boon Leong <boon.leong.ong-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>\n" + "> Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>\n" + "> Signed-off-by: Ong, Boon Leong <boon.leong.ong@intel.com>\n" "> ---\n" "> drivers/i2c/busses/i2c-designware-pcidrv.c | 17 +++++++++++------\n" "> 1 files changed, 11 insertions(+), 6 deletions(-)\n" @@ -67,4 +66,4 @@ "=v7HB\n" "-----END PGP SIGNATURE-----\n" -2ac874547d65c72fe30366047bb2837132289cdcaa9898e6320ec9d025eba71b +d9a9c3cbd611da5552d024b54b0fbde9ab351e6de367255463a409b03a834ab0
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