From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH] drm/i915/bdw: The TLB invalidation mechanism has been removed from INSTPM Date: Thu, 13 Mar 2014 03:52:54 +0100 Message-ID: <20140313025254.GO30571@phenom.ffwll.local> References: <1394674828-12129-1-git-send-email-damien.lespiau@intel.com> <20140313022145.GA5634@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ee0-f41.google.com (mail-ee0-f41.google.com [74.125.83.41]) by gabe.freedesktop.org (Postfix) with ESMTP id 5C58FFACBB for ; Wed, 12 Mar 2014 19:52:59 -0700 (PDT) Received: by mail-ee0-f41.google.com with SMTP id t10so135309eei.14 for ; Wed, 12 Mar 2014 19:52:58 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20140313022145.GA5634@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Ben Widawsky Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, Mar 12, 2014 at 07:21:45PM -0700, Ben Widawsky wrote: > On Thu, Mar 13, 2014 at 01:40:28AM +0000, Damien Lespiau wrote: > > While wandering in the spec, I noticed that BDW removes those 2 bits > > from INSTPM. I couldn't find any direct way to invalidate the TLB (ie > > without the ring working already). Maybe someone will be more lucky. > > > > At least, we now know we may be a problem. > > > > Signed-off-by: Damien Lespiau > > --- > > drivers/gpu/drm/i915/intel_ringbuffer.c | 10 ++++++++-- > > 1 file changed, 8 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > > index c50388a..4eb3e06 100644 > > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > > @@ -981,8 +981,14 @@ void intel_ring_setup_status_page(struct intel_ring_buffer *ring) > > I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); > > POSTING_READ(mmio); > > > > - /* Flush the TLB for this page */ > > - if (INTEL_INFO(dev)->gen >= 6) { > > + /* > > + * Flush the TLB for this page > > + * > > + * FIXME: These two bits have disappeared on gen8, so a question > > + * arises: do we still need this and if so how should we go about > > + * invalidating the TLB? > > + */ > > + if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) { > > u32 reg = RING_INSTPM(ring->mmio_base); > > > > /* ring should be idle before issuing a sync flush*/ > > I'm missing something on the original patch, > 884020bf3d2a3787a1cc6df902e98e0eec60330b. How were we emitting > breadcrumbs without flushing the TLB? All bathcbuffers should be > bookended by a TLB invalidate already, so I'm not sure the logic holds. > Chris could explain that one a bit further? > > The only reason I bring this up is I'd like to rip this out completely > and have Thiago retest, or at least change the comment/commit message to > be to reflect whatever light Chris sheds on the matter. > > Anyway, the bits are definitely gone, and I also can't find a non-ring > based replacement. > Reviewed-by: Ben Widawsky Queued for -next, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch