diff for duplicates of <20140318102435.2d29abc7@xhacker> diff --git a/a/1.txt b/N1/1.txt index e7e9422..74f12c9 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,13 +1,13 @@ Hi Antoine, On Mon, 17 Mar 2014 08:06:26 -0700 -Antoine T?nart <antoine.tenart@free-electrons.com> wrote: +Antoine Ténart <antoine.tenart@free-electrons.com> wrote: > Adds initial support for the Marvell Armada 1500 pro (BG2Q) SoC (Berlin > family). The SoC has nodes for cpu, l2 cache controller, interrupt > controllers, local timer, apb timers and uarts for now. > -> Signed-off-by: Antoine T?nart <antoine.tenart@free-electrons.com> +> Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com> > Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> > --- > arch/arm/boot/dts/berlin2q.dtsi | 210 @@ -21,7 +21,7 @@ Antoine T?nart <antoine.tenart@free-electrons.com> wrote: > +++ b/arch/arm/boot/dts/berlin2q.dtsi > @@ -0,0 +1,210 @@ > +/* -> + * Copyright (C) 2014 Antoine T?nart <antoine.tenart@free-electrons.com> +> + * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com> > + * > + * This file is licensed under the terms of the GNU General Public > + * License version 2. This program is licensed "as is" without any @@ -40,28 +40,28 @@ Antoine T?nart <antoine.tenart@free-electrons.com> wrote: > + #address-cells = <1>; > + #size-cells = <0>; > + -> + cpu at 0 { +> + cpu@0 { > + compatible = "arm,cortex-a9"; > + device_type = "cpu"; > + next-level-cache = <&l2>; > + reg = <0>; > + }; > + -> + cpu at 1 { +> + cpu@1 { > + compatible = "arm,cortex-a9"; > + device_type = "cpu"; > + next-level-cache = <&l2>; > + reg = <1>; > + }; > + -> + cpu at 2 { +> + cpu@2 { > + compatible = "arm,cortex-a9"; > + device_type = "cpu"; > + next-level-cache = <&l2>; > + reg = <2>; > + }; > + -> + cpu at 3 { +> + cpu@3 { > + compatible = "arm,cortex-a9"; > + device_type = "cpu"; > + next-level-cache = <&l2>; diff --git a/a/content_digest b/N1/content_digest index ad14856..523ceb9 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,21 +1,26 @@ "ref\01395068788-19786-1-git-send-email-antoine.tenart@free-electrons.com\0" "ref\01395068788-19786-2-git-send-email-antoine.tenart@free-electrons.com\0" - "From\0jszhang@marvell.com (Jisheng Zhang)\0" - "Subject\0[PATCH v3 1/3] ARM: dts: berlin2q: add the Marvell Armada 1500 pro\0" + "From\0Jisheng Zhang <jszhang@marvell.com>\0" + "Subject\0Re: [PATCH v3 1/3] ARM: dts: berlin2q: add the Marvell Armada 1500 pro\0" "Date\0Tue, 18 Mar 2014 10:24:35 +0800\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Antoine T\303\251nart <antoine.tenart@free-electrons.com>\0" + "Cc\0sebastian.hesselbarth@gmail.com <sebastian.hesselbarth@gmail.com>" + Jimmy Xu <zmxu@marvell.com> + linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org> + alexandre.belloni@free-electrons.com <alexandre.belloni@free-electrons.com> + " linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>\0" "\00:1\0" "b\0" "Hi Antoine,\n" "\n" "On Mon, 17 Mar 2014 08:06:26 -0700\n" - "Antoine T?nart <antoine.tenart@free-electrons.com> wrote:\n" + "Antoine T\303\251nart <antoine.tenart@free-electrons.com> wrote:\n" "\n" "> Adds initial support for the Marvell Armada 1500 pro (BG2Q) SoC (Berlin\n" "> family). The SoC has nodes for cpu, l2 cache controller, interrupt\n" "> controllers, local timer, apb timers and uarts for now.\n" "> \n" - "> Signed-off-by: Antoine T?nart <antoine.tenart@free-electrons.com>\n" + "> Signed-off-by: Antoine T\303\251nart <antoine.tenart@free-electrons.com>\n" "> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>\n" "> ---\n" "> arch/arm/boot/dts/berlin2q.dtsi | 210\n" @@ -29,7 +34,7 @@ "> +++ b/arch/arm/boot/dts/berlin2q.dtsi\n" "> @@ -0,0 +1,210 @@\n" "> +/*\n" - "> + * Copyright (C) 2014 Antoine T?nart <antoine.tenart@free-electrons.com>\n" + "> + * Copyright (C) 2014 Antoine T\303\251nart <antoine.tenart@free-electrons.com>\n" "> + *\n" "> + * This file is licensed under the terms of the GNU General Public\n" "> + * License version 2. This program is licensed \"as is\" without any\n" @@ -48,28 +53,28 @@ "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\tcpu at 0 {\n" + "> +\t\tcpu@0 {\n" "> +\t\t\tcompatible = \"arm,cortex-a9\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tnext-level-cache = <&l2>;\n" "> +\t\t\treg = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 1 {\n" + "> +\t\tcpu@1 {\n" "> +\t\t\tcompatible = \"arm,cortex-a9\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tnext-level-cache = <&l2>;\n" "> +\t\t\treg = <1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 2 {\n" + "> +\t\tcpu@2 {\n" "> +\t\t\tcompatible = \"arm,cortex-a9\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tnext-level-cache = <&l2>;\n" "> +\t\t\treg = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 3 {\n" + "> +\t\tcpu@3 {\n" "> +\t\t\tcompatible = \"arm,cortex-a9\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tnext-level-cache = <&l2>;\n" @@ -100,4 +105,4 @@ "Can you please name it as twdclk to avoid confusion? On Berlin, sysclk is another\n" clk rather than the clk for twd. -b401ce2bfb8d5b5267db203047364129dc38805a559a7c59101c9df59d93fca0 +701e0cb32e411da89a3779436fdd295b707f33d4103401b2f5e5bd10a8df8599
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