From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ben Widawsky Subject: Re: [PATCH 14/20] drm/i915: enable SDEIER later Date: Tue, 18 Mar 2014 13:29:13 -0700 Message-ID: <20140318202912.GE28915@bwidawsk.net> References: <1394233836-3827-1-git-send-email-przanoni@gmail.com> <1394233836-3827-15-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail.bwidawsk.net (bwidawsk.net [166.78.191.112]) by gabe.freedesktop.org (Postfix) with ESMTP id 6E0CA6FB19 for ; Tue, 18 Mar 2014 13:29:27 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1394233836-3827-15-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Paulo Zanoni Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org On Fri, Mar 07, 2014 at 08:10:30PM -0300, Paulo Zanoni wrote: > From: Paulo Zanoni > > On the preinstall stage we should just disable all the interrupts, but > we currently enable all the south display interrupts due to the way we > touch SDEIER at the IRQ handlers (note: they are still masked and our > IRQ handler is disabled). I think this statement is false. The interrupt is enabled right after preinstall(). For the nomodeset case, this actually seems to make some difference. It still looks fine to me though. > Instead of doing that, let's make the > preinstall stage just disable all the south interrupts, and do the > proper interrupt dance/ordering at the postinstall stage, including an > assert to check if everything is behaving as expected. > > Signed-off-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/i915_irq.c | 27 +++++++++++++++++++++------ > 1 file changed, 21 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 95f535b..4479e29 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -2814,13 +2814,24 @@ static void ibx_irq_preinstall(struct drm_device *dev) > > if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) > I915_WRITE(SERR_INT, 0xffffffff); > +} > > - /* > - * SDEIER is also touched by the interrupt handler to work around missed > - * PCH interrupts. Hence we can't update it after the interrupt handler > - * is enabled - instead we unconditionally enable all PCH interrupt > - * sources here, but then only unmask them as needed with SDEIMR. > - */ > +/* > + * SDEIER is also touched by the interrupt handler to work around missed PCH > + * interrupts. Hence we can't update it after the interrupt handler is enabled - > + * instead we unconditionally enable all PCH interrupt sources here, but then > + * only unmask them as needed with SDEIMR. > + * > + * This function needs to be called before interrupts are enabled. > + */ > +static void ibx_irq_pre_postinstall(struct drm_device *dev) sde_irq_postinstall()? > +{ > + struct drm_i915_private *dev_priv = dev->dev_private; > + > + if (HAS_PCH_NOP(dev)) > + return; > + > + WARN_ON(I915_READ(SDEIER) != 0); > I915_WRITE(SDEIER, 0xffffffff); > POSTING_READ(SDEIER); > } > @@ -3026,6 +3037,8 @@ static int ironlake_irq_postinstall(struct drm_device *dev) > > dev_priv->irq_mask = ~display_mask; > > + ibx_irq_pre_postinstall(dev); > + > GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); > > gen5_gt_irq_postinstall(dev); > @@ -3217,6 +3230,8 @@ static int gen8_irq_postinstall(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > > + ibx_irq_pre_postinstall(dev); > + > gen8_gt_irq_postinstall(dev_priv); > gen8_de_irq_postinstall(dev_priv); > > -- > 1.8.5.3 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ben Widawsky, Intel Open Source Technology Center