From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/i915/vlv: use W_SYNC_SHIFT for interlaced modes on VLV Date: Fri, 28 Mar 2014 21:49:27 +0200 Message-ID: <20140328194927.GS21652@intel.com> References: <1395946568-24618-1-git-send-email-jbarnes@virtuousgeek.org> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id CA94C6E734 for ; Fri, 28 Mar 2014 12:49:34 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1395946568-24618-1-git-send-email-jbarnes@virtuousgeek.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, Mar 27, 2014 at 11:56:08AM -0700, Jesse Barnes wrote: > This makes HDMI testers happier on VLV platforms. It may be that we > need it for any non-SVO platform, but I don't have any tests to back > that up, so I'm leaving other pre-ILK platforms alone for now. It looks like we should use PIPECONF_INTERLACE_W_FIELD_INDICATION only with sdvo on gen4+, and always on gen3 (simply because VSYNCSHIFT didn't yet exist). Oh and we seem to misprogram VSYNCSHIFT on ILK+ with SDVO. The correct value would be htotal/2 instead of the midway point between hsync pulses. That's the value PIPECONF_INTERLACE_W_FIELD_INDICATION also implies, but ILK+ no longer has that option in PIPECONF, so VSYNCSHIFT must be progammed manually. > = > Tested-by: "Clint Taylor " > Signed-off-by: Jesse Barnes > --- > drivers/gpu/drm/i915/intel_display.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > = > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/= intel_display.c > index e0a87aa..d633139 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -5541,8 +5541,11 @@ static void i9xx_set_pipeconf(struct intel_crtc *i= ntel_crtc) > } > } > = > - if (!IS_GEN2(dev) && > + if (IS_VALLEYVIEW(dev) && > intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) > + pipeconf |=3D PIPECONF_INTERLACE_W_SYNC_SHIFT; > + else if (!IS_GEN2(dev) && > + intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) > pipeconf |=3D PIPECONF_INTERLACE_W_FIELD_INDICATION; > else > pipeconf |=3D PIPECONF_PROGRESSIVE; > -- = > 1.7.9.5PIPECONF_PROGRESSIVE > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC