Re: [PATCH] i2c-designware: Mask interrupts during i2c controller enable

["Westerberg, Mika" <mika.westerberg@intel.com>]

On Mon, Apr 07, 2014 at 03:42:52PM +0100, One Thousand Gnomes wrote:
> > I had to check BYT specs about that and I couldn't find if it does
> > posted-writes. 
> 
> Then I would assume it does unless you can find a hardware engineer to
> sign a statement in blood to that effect 8)

Fair enough.

> > Actually the following patch should fix the problem as well. Just move the
> > HW enable to happen last. That way we can make sure that there is a valid
> > interrupt mask programmed before the controller is enabled.
> 
> This fixes the init case, it doesn't fix the question about returning
> from the IRQ before the mask write takes effect and thus taking another
> interrupt.

Do you think we can fix it with adding a dummy read right after write to
the mask register, like the snippet below?

diff --git a/drivers/i2c/busses/i2c-designware-core.c b/drivers/i2c/busses/i2c-designware-core.c
index 14c4b30d4ccc..ff9090381d8b 100644
--- a/drivers/i2c/busses/i2c-designware-core.c
+++ b/drivers/i2c/busses/i2c-designware-core.c
@@ -535,6 +535,7 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
 		intr_mask = 0;
 
 	dw_writel(dev, intr_mask,  DW_IC_INTR_MASK);
+	dw_readl(dev, DW_IC_INTR_MASK);
 }
 
 static void