All of lore.kernel.org
 help / color / mirror / Atom feed
diff for duplicates of <20140408233202.GM9985@codeaurora.org>

diff --git a/a/1.txt b/N1/1.txt
index b4830eb..f469500 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -25,7 +25,7 @@ compatible in each cpu node even though it's always the same.
 
 > +		enable-method = "qcom,kpss-acc-v1";
 > +
-> +		cpu@0 {
+> +		cpu at 0 {
 > +			device_type = "cpu";
 > +			reg = <0>;
 > +			next-level-cache = <&L2>;
@@ -33,7 +33,7 @@ compatible in each cpu node even though it's always the same.
 > +			qcom,saw = <&saw0>;
 > +		};
 > +
-> +		cpu@1 {
+> +		cpu at 1 {
 > +			device_type = "cpu";
 > +			reg = <1>;
 > +			next-level-cache = <&L2>;
@@ -41,7 +41,7 @@ compatible in each cpu node even though it's always the same.
 > +			qcom,saw = <&saw1>;
 > +		};
 > +
-> +		cpu@2 {
+> +		cpu at 2 {
 > +			device_type = "cpu";
 > +			reg = <2>;
 > +			next-level-cache = <&L2>;
@@ -49,7 +49,7 @@ compatible in each cpu node even though it's always the same.
 > +			qcom,saw = <&saw2>;
 > +		};
 > +
-> +		cpu@3 {
+> +		cpu at 3 {
 > +			device_type = "cpu";
 > +			reg = <3>;
 > +			next-level-cache = <&L2>;
@@ -85,7 +85,7 @@ These interrupts here are also not accepted as a binding yet.
 
 Nit: Weird two newlines here
 
-> +		intc: interrupt-controller@2000000 {
+> +		intc: interrupt-controller at 2000000 {
 > +			compatible = "qcom,msm-qgic2";
 > +			interrupt-controller;
 > +			#interrupt-cells = <3>;
diff --git a/a/content_digest b/N1/content_digest
index f358317..0914e0f 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,18 +1,8 @@
  "ref\01396972391-11759-1-git-send-email-galak@codeaurora.org\0"
- "From\0Stephen Boyd <sboyd@codeaurora.org>\0"
- "Subject\0Re: [PATCH v2] ARM: qcom: Add initial APQ8064 SoC and IFC6410 board device trees\0"
+ "From\0sboyd@codeaurora.org (Stephen Boyd)\0"
+ "Subject\0[PATCH v2] ARM: qcom: Add initial APQ8064 SoC and IFC6410 board device trees\0"
  "Date\0Tue, 8 Apr 2014 16:32:02 -0700\0"
- "To\0Kumar Gala <galak@codeaurora.org>\0"
- "Cc\0Rob Herring <robh+dt@kernel.org>"
-  Pawel Moll <pawel.moll@arm.com>
-  Mark Rutland <mark.rutland@arm.com>
-  Ian Campbell <ijc+devicetree@hellion.org.uk>
-  Russell King <linux@arm.linux.org.uk>
-  David Brown <davidb@codeaurora.org>
-  devicetree@vger.kernel.org
-  linux-kernel@vger.kernel.org
-  linux-arm-kernel@lists.infradead.org
- " linux-arm-msm@vger.kernel.org\0"
+ "To\0linux-arm-kernel@lists.infradead.org\0"
  "\00:1\0"
  "b\0"
  "On 04/08, Kumar Gala wrote:\n"
@@ -42,7 +32,7 @@
  "\n"
  "> +\t\tenable-method = \"qcom,kpss-acc-v1\";\n"
  "> +\n"
- "> +\t\tcpu@0 {\n"
+ "> +\t\tcpu at 0 {\n"
  "> +\t\t\tdevice_type = \"cpu\";\n"
  "> +\t\t\treg = <0>;\n"
  "> +\t\t\tnext-level-cache = <&L2>;\n"
@@ -50,7 +40,7 @@
  "> +\t\t\tqcom,saw = <&saw0>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tcpu@1 {\n"
+ "> +\t\tcpu at 1 {\n"
  "> +\t\t\tdevice_type = \"cpu\";\n"
  "> +\t\t\treg = <1>;\n"
  "> +\t\t\tnext-level-cache = <&L2>;\n"
@@ -58,7 +48,7 @@
  "> +\t\t\tqcom,saw = <&saw1>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tcpu@2 {\n"
+ "> +\t\tcpu at 2 {\n"
  "> +\t\t\tdevice_type = \"cpu\";\n"
  "> +\t\t\treg = <2>;\n"
  "> +\t\t\tnext-level-cache = <&L2>;\n"
@@ -66,7 +56,7 @@
  "> +\t\t\tqcom,saw = <&saw2>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tcpu@3 {\n"
+ "> +\t\tcpu at 3 {\n"
  "> +\t\t\tdevice_type = \"cpu\";\n"
  "> +\t\t\treg = <3>;\n"
  "> +\t\t\tnext-level-cache = <&L2>;\n"
@@ -102,7 +92,7 @@
  "\n"
  "Nit: Weird two newlines here\n"
  "\n"
- "> +\t\tintc: interrupt-controller@2000000 {\n"
+ "> +\t\tintc: interrupt-controller at 2000000 {\n"
  "> +\t\t\tcompatible = \"qcom,msm-qgic2\";\n"
  "> +\t\t\tinterrupt-controller;\n"
  "> +\t\t\t#interrupt-cells = <3>;\n"
@@ -115,4 +105,4 @@
  "Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,\n"
  hosted by The Linux Foundation
 
-9182ec4e2944a6da283f17ebacfc64964e2ace1f666dbb867ebf47d9cb696c5c
+df295cf23ac7fb809af20cae4471e75610eb9131b86cf5132d99c653d8b11efc

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.