Re: [Qemu-devel] [PATCH microblaze v1 1/1] net: xilinx_axienet.c: Add phy soft reset bit clearing

[Beniamino Galvani <b.galvani@gmail.com>]

On Tue, Apr 08, 2014 at 06:52:39PM -0700, Peter Crosthwaite wrote:
> From: Nathan Rossi <nathan.rossi@xilinx.com>
> 
> Clear the BMCR Reset when writing to registers.
> 
> Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com>
> [ PC:
>  * Trivial style fixes to commit message
> ]
> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
> ---
> 
>  hw/net/xilinx_axienet.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
> index 839d97c..0f485a0 100644
> --- a/hw/net/xilinx_axienet.c
> +++ b/hw/net/xilinx_axienet.c
> @@ -142,6 +142,9 @@ tdk_write(struct PHY *phy, unsigned int req, unsigned int data)
>              phy->regs[regnum] = data;
>              break;
>      }
> +
> +    /* Unconditionally clear regs[BMCR][BMCR_RESET] */
> +    phy->regs[0] &= ~0x8000;
>  }
>  
>  static void
> -- 

Reviewed-by: Beniamino Galvani <b.galvani@gmail.com>

Ideally we should also restore default values of registers after a
reset, but probably it is not required for the guest to operate
properly.

Beniamino