Re: [PATCH] drm/i915/bdw: BDW swizzling in done by the memory controller

[Daniel Vetter <daniel@ffwll.ch>]

On Thu, Apr 10, 2014 at 05:24:08PM +0100, Damien Lespiau wrote:
> Instead of needing to configure swizzling in 3 units (GAM, GT, DE), the
> memory controller is in charge of doing them on BDW. As a consequence
> all those swizzling bits are reserved. As specs put it:
> 
>   Before Gen8, there was a historical configuration control field to
>   swizzle address bit[6] for in X/Y tiling modes. This was set in three
>   different places: TILECTL[1:0], ARB_MODE[5:4], and
>   DISP_ARB_CTL[14:13]"
> 
>   For Gen8 the swizzle fields are all reserved, and the CPU's memory
>   controller performs all address swizzling modifications.
> 
> This also means that user space doesn't have to manually swizzle when
> accessing tiled buffers from the CPU, and so we always return
> I915_BIT_6_SWIZZLE_NONE from i915_gem_detect_bit_6_swizzle(), which
> short-circuits the initialization of the registers mentionned above in
> i915_gem_init_swizzling().
> 
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>

Afaik the memory controller has always done the swizzling. What this pile
of bits controls is the _additional_ swizzling done to improve the access
pattern for 2d data, i.e. everything X and Y tiled. The theory of
operation is that the additional swizzling improves access patterns when
walking in Y direction on a surface.

And when we've last looked at this (well Chris) it seemed to indeed have
improved sampler performace. The downside is that it's a bit a pain for
userspace since essentially userspace has to deal with 4 tiling formats
instead of just 2, but we have all the code for that.

So not yet sold on the story here, at least for gen8/bdw. Apparently
people haven't screamed about this yet, so it probably works.
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_gem.c        |  2 --
>  drivers/gpu/drm/i915/i915_gem_tiling.c | 10 +++++++++-
>  drivers/gpu/drm/i915/i915_reg.h        |  1 -
>  3 files changed, 9 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 85c9cf0..9032c1b 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4325,8 +4325,6 @@ void i915_gem_init_swizzling(struct drm_device *dev)
>  		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
>  	else if (IS_GEN7(dev))
>  		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
> -	else if (IS_GEN8(dev))
> -		I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
>  	else
>  		BUG();
>  }
> diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
> index cb150e8..a5ddf12 100644
> --- a/drivers/gpu/drm/i915/i915_gem_tiling.c
> +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
> @@ -91,7 +91,15 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
>  	uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
>  	uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
>  
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (INTEL_INFO(dev)->gen >= 8) {
> +		/*
> +		 * On BDW+, the CPU memory controller performs all address
> +		 * swizzling modifications. This condition also catches CHV,
> +		 * where swizzling is not supported.
> +		 */
> +		swizzle_x = I915_BIT_6_SWIZZLE_NONE;
> +		swizzle_y = I915_BIT_6_SWIZZLE_NONE;
> +	} else if (IS_VALLEYVIEW(dev)) {
>  		swizzle_x = I915_BIT_6_SWIZZLE_NONE;
>  		swizzle_y = I915_BIT_6_SWIZZLE_NONE;
>  	} else if (INTEL_INFO(dev)->gen >= 6) {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 01c05af..faba21b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -781,7 +781,6 @@ enum punit_power_well {
>  #define   ARB_MODE_SWIZZLE_IVB	(1<<5)
>  #define GAMTARBMODE		0x04a08
>  #define   ARB_MODE_BWGTLB_DISABLE (1<<9)
> -#define   ARB_MODE_SWIZZLE_BDW	(1<<1)
>  #define RENDER_HWS_PGA_GEN7	(0x04080)
>  #define RING_FAULT_REG(ring)	(0x4094 + 0x100*(ring)->id)
>  #define   RING_FAULT_GTTSEL_MASK (1<<11)
> -- 
> 1.8.3.1
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch