Re: [PATCH V2] i2c-designware: Mask all interrupts during i2c controller enable

["Westerberg, Mika" <mika.westerberg@intel.com>]

On Fri, Apr 11, 2014 at 02:03:19AM +0300, Du, Wenkai wrote:
> Hi all,
> 
> Updated problem descriptions from Mika's feedback and new test data: 
> 
> There have been "i2c_designware 80860F41:00: controller timed out" errors
> on a number of Baytrail platforms. The issue is caused by incorrect value in
> Interrupt Mask Register (DW_IC_INTR_MASK)  when i2c core is being enabled. 
> This causes call to __i2c_dw_enable() to immediately start the transfer which
> leads to timeout. There are 3 failure modes observed:
> 
> 1. Failure in S0 to S3 resume path
> 
> The default value after reset for DW_IC_INTR_MASK is 0x8ff. When we start 
> the first transaction after resuming from system sleep, TX_EMPTY interrupt 
> is already unmasked because of the hardware default.
> 
> 2. Failure in normal operational path
> 
> This failure happens rarely and is hard to reproduce. Debug trace showed that
> DW_IC_INTR_MASK had value of 0x254 when failure occurred, which meant 
> TX_EMPTY was unmasked.
> 
> 2. Failure in S3 to S0 suspend path

This should probably be 3.

> This failure also happens rarely and is hard to reproduce. Adding debug trace
> that read DW_IC_INTR_MASK made this failure not reproducible. But from ISR 
> call trace we could conclude TX_EMPTY was unmasked when problem occurred.
> 
> 
> The patch masks all interrupts before the controller is enabled to resolve the
> faulty DW_IC_INTR_MASK conditions.
> 
> Signed-off-by: Wenkai Du <wenkai.du@intel.com>

Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>