diff for duplicates of <20140411163228.4214645c@skate> diff --git a/a/1.txt b/N1/1.txt index 0913e8e..00057d0 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -39,3 +39,101 @@ Thomas Thomas Petazzoni, CTO, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com +-------------- next part -------------- +A non-text attachment was scrubbed... +Name: 0001-igb-Fix-Null-pointer-dereference-in-igb_reset_q_vect.patch +Type: text/x-patch +Size: 1808 bytes +Desc: not available +URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140411/1b58ef39/attachment-0014.bin> +-------------- next part -------------- +A non-text attachment was scrubbed... +Name: 0002-igb-Unset-IGB_FLAG_HAS_MSIX-flag-when-falling-back-t.patch +Type: text/x-patch +Size: 5116 bytes +Desc: not available +URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140411/1b58ef39/attachment-0015.bin> +-------------- next part -------------- +A non-text attachment was scrubbed... +Name: 0003-ARM-mvebu-change-the-default-PCIe-apertures-for-Arma.patch +Type: text/x-patch +Size: 2556 bytes +Desc: not available +URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140411/1b58ef39/attachment-0016.bin> +-------------- next part -------------- +A non-text attachment was scrubbed... +Name: 0004-ARM-mvebu-switch-the-Armada-XP-DB-to-use-internal-re.patch +Type: text/x-patch +Size: 2498 bytes +Desc: not available +URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140411/1b58ef39/attachment-0017.bin> +-------------- next part -------------- +A non-text attachment was scrubbed... +Name: 0005-ARM-mvebu-switch-the-Armada-XP-GP-to-use-internal-re.patch +Type: text/x-patch +Size: 3574 bytes +Desc: not available +URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140411/1b58ef39/attachment-0018.bin> +-------------- next part -------------- +A non-text attachment was scrubbed... +Name: 0006-irqchip-armada-370-xp-fix-invalid-cast-of-signed-val.patch +Type: text/x-patch +Size: 1377 bytes +Desc: not available +URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140411/1b58ef39/attachment-0019.bin> +-------------- next part -------------- +A non-text attachment was scrubbed... +Name: 0007-irqchip-armada-370-xp-implement-the-check_device-msi.patch +Type: text/x-patch +Size: 1700 bytes +Desc: not available +URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140411/1b58ef39/attachment-0020.bin> +-------------- next part -------------- +A non-text attachment was scrubbed... +Name: 0008-irqchip-armada-370-xp-Fix-releasing-of-MSIs.patch +Type: text/x-patch +Size: 1273 bytes +Desc: not available +URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140411/1b58ef39/attachment-0021.bin> +-------------- next part -------------- +A non-text attachment was scrubbed... +Name: 0009-pci-mvebu-fix-off-by-one-in-the-computed-size-of-the.patch +Type: text/x-patch +Size: 1860 bytes +Desc: not available +URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140411/1b58ef39/attachment-0022.bin> +-------------- next part -------------- +A non-text attachment was scrubbed... +Name: 0010-bus-mvebu-mbus-Avoid-setting-an-undefined-window-siz.patch +Type: text/x-patch +Size: 2238 bytes +Desc: not available +URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140411/1b58ef39/attachment-0023.bin> +-------------- next part -------------- +A non-text attachment was scrubbed... +Name: 0011-bus-mvebu-mbus-allow-several-windows-with-the-same-t.patch +Type: text/x-patch +Size: 1136 bytes +Desc: not available +URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140411/1b58ef39/attachment-0024.bin> +-------------- next part -------------- +A non-text attachment was scrubbed... +Name: 0012-pci-pci-mvebu-split-PCIe-BARs-into-multiple-MBus-win.patch +Type: text/x-patch +Size: 6126 bytes +Desc: not available +URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140411/1b58ef39/attachment-0025.bin> +-------------- next part -------------- +A non-text attachment was scrubbed... +Name: 0013-pci-pci-mvebu-wait-for-a-device-to-appear-to-fix-clo.patch +Type: text/x-patch +Size: 3592 bytes +Desc: not available +URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140411/1b58ef39/attachment-0026.bin> +-------------- next part -------------- +A non-text attachment was scrubbed... +Name: combined.patch +Type: text/x-patch +Size: 15073 bytes +Desc: not available +URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140411/1b58ef39/attachment-0027.bin> diff --git a/a/10.hdr b/a/10.hdr deleted file mode 100644 index 5a05664..0000000 --- a/a/10.hdr +++ /dev/null @@ -1,4 +0,0 @@ -Content-Type: text/x-patch -Content-Transfer-Encoding: 7bit -Content-Disposition: attachment; - filename=0009-pci-mvebu-fix-off-by-one-in-the-computed-size-of-the.patch diff --git a/a/10.txt b/a/10.txt deleted file mode 100644 index ac80628..0000000 --- a/a/10.txt +++ /dev/null @@ -1,47 +0,0 @@ ->From 7c1f808988da77a1d315459f735609426abb2c41 Mon Sep 17 00:00:00 2001 -From: Willy Tarreau <w@1wt.eu> -Date: Wed, 9 Apr 2014 08:05:09 +0200 -Subject: [PATCH 09/13] pci: mvebu: fix off-by-one in the computed size of the - mbus windows - -mvebu_pcie_handle_membase_change() and -mvebu_pcie_handle_iobase_change() do not correctly compute the window -size. PCI uses an inclusive start/end address pair, which requires a -+1 when converting to size. - -This only worked because a bug in the mbus driver allowed it to -silently accept and round up bogus sizes. - -Fix this by adding one to the computed size. - -Signed-off-by: Willy Tarreau <w@1wt.eu> -Reviewed-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> -Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> ---- - drivers/pci/host/pci-mvebu.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c -index 0e79665..eff0ab5 100644 ---- a/drivers/pci/host/pci-mvebu.c -+++ b/drivers/pci/host/pci-mvebu.c -@@ -329,7 +329,7 @@ static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port) - port->iowin_base = port->pcie->io.start + iobase; - port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) | - (port->bridge.iolimitupper << 16)) - -- iobase); -+ iobase) + 1; - - mvebu_mbus_add_window_remap_by_id(port->io_target, port->io_attr, - port->iowin_base, port->iowin_size, -@@ -362,7 +362,7 @@ static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port) - port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16); - port->memwin_size = - (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) - -- port->memwin_base; -+ port->memwin_base + 1; - - mvebu_mbus_add_window_by_id(port->mem_target, port->mem_attr, - port->memwin_base, port->memwin_size); --- -1.8.3.2 diff --git a/a/11.hdr b/a/11.hdr deleted file mode 100644 index cf428b5..0000000 --- a/a/11.hdr +++ /dev/null @@ -1,4 +0,0 @@ -Content-Type: text/x-patch -Content-Transfer-Encoding: 7bit -Content-Disposition: attachment; - filename=0010-bus-mvebu-mbus-Avoid-setting-an-undefined-window-siz.patch diff --git a/a/11.txt b/a/11.txt deleted file mode 100644 index a44b529..0000000 --- a/a/11.txt +++ /dev/null @@ -1,66 +0,0 @@ ->From e3eaec9f807213a6321c44780a09187c93f0145a Mon Sep 17 00:00:00 2001 -From: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> -Date: Tue, 8 Apr 2014 17:44:14 -0600 -Subject: [PATCH 10/13] bus: mvebu-mbus: Avoid setting an undefined window size - -The mbus hardware requires a power of two size, and size aligned base. -Currently, if a non-power of two is passed in to the low level routines -they configure the register in a way that results in undefined behaviour. - -Call WARN and return EINVAL instead. - -Also, update the debugfs routines to show a message if there is an -invalid register setting. - -All together this makes the recent problems with silent failure -of PCI very obvious, noisy and debuggable. - -Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> -Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> ---- - drivers/bus/mvebu-mbus.c | 16 ++++++++++++++++ - 1 file changed, 16 insertions(+) - -diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c -index 725c461..15a398d 100644 ---- a/drivers/bus/mvebu-mbus.c -+++ b/drivers/bus/mvebu-mbus.c -@@ -56,6 +56,7 @@ - #include <linux/of.h> - #include <linux/of_address.h> - #include <linux/debugfs.h> -+#include <linux/log2.h> - - /* - * DDR target is the same on all platforms. -@@ -266,6 +267,17 @@ static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus, - mbus->soc->win_cfg_offset(win); - u32 ctrl, remap_addr; - -+ if (!is_power_of_2(size)) { -+ WARN(true, "Invalid MBus window size: 0x%zx\n", size); -+ return -EINVAL; -+ } -+ -+ if ((base & (phys_addr_t)(size - 1)) != 0) { -+ WARN(true, "Invalid MBus base/size: %pa len 0x%zx\n", &base, -+ size); -+ return -EINVAL; -+ } -+ - ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) | - (attr << WIN_CTRL_ATTR_SHIFT) | - (target << WIN_CTRL_TGT_SHIFT) | -@@ -413,6 +425,10 @@ static int mvebu_devs_debug_show(struct seq_file *seq, void *v) - win, (unsigned long long)wbase, - (unsigned long long)(wbase + wsize), wtarget, wattr); - -+ if (!is_power_of_2(wsize) || -+ ((wbase & (u64)(wsize - 1)) != 0)) -+ seq_puts(seq, " (Invalid base/size!!)"); -+ - if (win < mbus->soc->num_remappable_wins) { - seq_printf(seq, " (remap %016llx)\n", - (unsigned long long)wremap); --- -1.8.3.2 diff --git a/a/12.hdr b/a/12.hdr deleted file mode 100644 index 50a0a98..0000000 --- a/a/12.hdr +++ /dev/null @@ -1,4 +0,0 @@ -Content-Type: text/x-patch -Content-Transfer-Encoding: 7bit -Content-Disposition: attachment; - filename=0011-bus-mvebu-mbus-allow-several-windows-with-the-same-t.patch diff --git a/a/12.txt b/a/12.txt deleted file mode 100644 index e8a9d14..0000000 --- a/a/12.txt +++ /dev/null @@ -1,35 +0,0 @@ ->From d6184385d76474408ad9922be57d0d47525094e0 Mon Sep 17 00:00:00 2001 -From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> -Date: Thu, 10 Apr 2014 16:15:15 +0200 -Subject: [PATCH 11/13] bus: mvebu-mbus: allow several windows with the same - target/attribute - -Having multiple windows with the same target and attribute is actually -legal, and can be useful for PCIe windows, when PCIe BARs have a size -that isn't a power of two, and we therefore need to create several -MBus windows to cover the PCIe BAR for a given PCIe interface. - -Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> ---- - drivers/bus/mvebu-mbus.c | 6 ------ - 1 file changed, 6 deletions(-) - -diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c -index 15a398d..54d339e 100644 ---- a/drivers/bus/mvebu-mbus.c -+++ b/drivers/bus/mvebu-mbus.c -@@ -223,12 +223,6 @@ static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus, - */ - if ((u64)base < wend && end > wbase) - return 0; -- -- /* -- * Check if target/attribute conflicts -- */ -- if (target == wtarget && attr == wattr) -- return 0; - } - - return 1; --- -1.8.3.2 diff --git a/a/13.hdr b/a/13.hdr deleted file mode 100644 index e3ff92d..0000000 --- a/a/13.hdr +++ /dev/null @@ -1,4 +0,0 @@ -Content-Type: text/x-patch -Content-Transfer-Encoding: 7bit -Content-Disposition: attachment; - filename=0012-pci-pci-mvebu-split-PCIe-BARs-into-multiple-MBus-win.patch diff --git a/a/13.txt b/a/13.txt deleted file mode 100644 index edc4814..0000000 --- a/a/13.txt +++ /dev/null @@ -1,169 +0,0 @@ ->From d5c41e956a19f4f7c69bc002291a866f4ad3e145 Mon Sep 17 00:00:00 2001 -From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> -Date: Thu, 10 Apr 2014 16:16:16 +0200 -Subject: [PATCH 12/13] pci: pci-mvebu: split PCIe BARs into multiple MBus - windows when needed - -MBus windows are used on Marvell platforms to map certain peripherals -in the physical address space. In the PCIe context, MBus windows are -needed to map PCIe I/O and memory regions in the physical address. - -However, those MBus windows can only have power of two sizes, while -PCIe BAR do not necessarily guarantee this. For this reason, the -current pci-mvebu breaks on platforms where PCIe devices have BARs -that don't sum up to a power of two size at the emulated bridge level. - -This commit fixes this by allowing the pci-mvebu driver to create -multiple contiguous MBus windows (each having a power of two size) to -cover a given PCIe BAR. - -To achieve this, two functions are added: mvebu_pcie_add_windows() and -mvebu_pcie_del_windows() to respectively add and remove all the MBus -windows that are needed to map the provided PCIe region base and -size. The emulated PCI bridge code now calls those functions, instead -of directly calling the mvebu-mbus driver functions. - -Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> ---- - drivers/pci/host/pci-mvebu.c | 88 +++++++++++++++++++++++++++++++++++++------- - 1 file changed, 74 insertions(+), 14 deletions(-) - -diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c -index eff0ab5..487c926 100644 ---- a/drivers/pci/host/pci-mvebu.c -+++ b/drivers/pci/host/pci-mvebu.c -@@ -291,6 +291,58 @@ static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port, - return PCIBIOS_SUCCESSFUL; - } - -+/* -+ * Remove windows, starting from the largest ones to the smallest -+ * ones. -+ */ -+static void mvebu_pcie_del_windows(struct mvebu_pcie_port *port, -+ phys_addr_t base, size_t size) -+{ -+ while (size) { -+ size_t sz = 1 << (fls(size) - 1); -+ -+ mvebu_mbus_del_window(base, sz); -+ base += sz; -+ size -= sz; -+ } -+} -+ -+/* -+ * MBus windows can only have a power of two size, but PCI BARs do not -+ * have this constraint. Therefore, we have to split the PCI BAR into -+ * areas each having a power of two size. We start from the largest -+ * one (i.e highest order bit set in the size). -+ */ -+static void mvebu_pcie_add_windows(struct mvebu_pcie_port *port, -+ unsigned int target, unsigned int attribute, -+ phys_addr_t base, size_t size, -+ phys_addr_t remap) -+{ -+ size_t size_mapped = 0; -+ -+ while (size) { -+ size_t sz = 1 << (fls(size) - 1); -+ int ret; -+ -+ ret = mvebu_mbus_add_window_remap_by_id(target, attribute, base, -+ sz, remap); -+ if (ret) { -+ dev_err(&port->pcie->pdev->dev, -+ "Could not create MBus window at 0x%x, size 0x%x: %d\n", -+ base, sz, ret); -+ mvebu_pcie_del_windows(port, base - size_mapped, -+ size_mapped); -+ return; -+ } -+ -+ size -= sz; -+ size_mapped += sz; -+ base += sz; -+ if (remap != MVEBU_MBUS_NO_REMAP) -+ remap += sz; -+ } -+} -+ - static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port) - { - phys_addr_t iobase; -@@ -302,8 +354,8 @@ static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port) - - /* If a window was configured, remove it */ - if (port->iowin_base) { -- mvebu_mbus_del_window(port->iowin_base, -- port->iowin_size); -+ mvebu_pcie_del_windows(port, port->iowin_base, -+ port->iowin_size); - port->iowin_base = 0; - port->iowin_size = 0; - } -@@ -331,9 +383,9 @@ static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port) - (port->bridge.iolimitupper << 16)) - - iobase) + 1; - -- mvebu_mbus_add_window_remap_by_id(port->io_target, port->io_attr, -- port->iowin_base, port->iowin_size, -- iobase); -+ mvebu_pcie_add_windows(port, port->io_target, port->io_attr, -+ port->iowin_base, port->iowin_size, -+ iobase); - } - - static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port) -@@ -344,8 +396,8 @@ static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port) - - /* If a window was configured, remove it */ - if (port->memwin_base) { -- mvebu_mbus_del_window(port->memwin_base, -- port->memwin_size); -+ mvebu_pcie_del_windows(port, port->memwin_base, -+ port->memwin_size); - port->memwin_base = 0; - port->memwin_size = 0; - } -@@ -364,8 +416,9 @@ static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port) - (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) - - port->memwin_base + 1; - -- mvebu_mbus_add_window_by_id(port->mem_target, port->mem_attr, -- port->memwin_base, port->memwin_size); -+ mvebu_pcie_add_windows(port, port->mem_target, port->mem_attr, -+ port->memwin_base, port->memwin_size, -+ MVEBU_MBUS_NO_REMAP); - } - - /* -@@ -721,14 +774,21 @@ static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev, - - /* - * On the PCI-to-PCI bridge side, the I/O windows must have at -- * least a 64 KB size and be aligned on their size, and the -- * memory windows must have at least a 1 MB size and be -- * aligned on their size -+ * least a 64 KB size and the memory windows must have at -+ * least a 1 MB size. Moreover, MBus windows need to have a -+ * base address aligned on their size, and their size must be -+ * a power of two. This means that if the BAR doesn't have a -+ * power of two size, several MBus windows will actually be -+ * created. We need to ensure that the biggest MBus window -+ * (which will be the first one) is aligned on its size, which -+ * explains the rounddown_pow_of_two() being done here. - */ - if (res->flags & IORESOURCE_IO) -- return round_up(start, max_t(resource_size_t, SZ_64K, size)); -+ return round_up(start, max_t(resource_size_t, SZ_64K, -+ rounddown_pow_of_two(size))); - else if (res->flags & IORESOURCE_MEM) -- return round_up(start, max_t(resource_size_t, SZ_1M, size)); -+ return round_up(start, max_t(resource_size_t, SZ_1M, -+ rounddown_pow_of_two(size))); - else - return start; - } --- -1.8.3.2 diff --git a/a/14.hdr b/a/14.hdr deleted file mode 100644 index 5cec437..0000000 --- a/a/14.hdr +++ /dev/null @@ -1,4 +0,0 @@ -Content-Type: text/x-patch -Content-Transfer-Encoding: 7bit -Content-Disposition: attachment; - filename=0013-pci-pci-mvebu-wait-for-a-device-to-appear-to-fix-clo.patch diff --git a/a/14.txt b/a/14.txt deleted file mode 100644 index b753781..0000000 --- a/a/14.txt +++ /dev/null @@ -1,113 +0,0 @@ ->From 72706b22617da7ef8dcf1924f4c204383111401c Mon Sep 17 00:00:00 2001 -From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> -Date: Fri, 11 Apr 2014 15:22:36 +0200 -Subject: [PATCH 13/13] pci: pci-mvebu: wait for a device to appear to fix - clock issues - -With the introduction of the mvebu-soc-id mechanism in -arch/arm/mach-mvebu/, the PCIe clocks can be gated during early boot, -and then re-enabled later when the pci-mvebu driver gets -called. However, after the clock has been enabled, it takes some time -for the PCIe device to become visible: this is causing problems on -some platforms where PCIe devices may not be detected at boot time due -to this. - -To fix this, this commit introduces a simple loop that waits for a -valid device to actually show up on each PCIe interface for which the -link is up. - -It fixes a problem reported both by Gregory Clement and Neil -Greatorex, which were seeing all PCIe devices detected when -earlyprintk was enabled, but one of the device was missing when -earlyprintk was disabled. This was due to the fact that earlyprintk -was slowing down the boot sufficiently to make the problem invisible. - -Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> -Reported-by: Neil Greatorex <neil@fatboyfat.co.uk> -Reported-by: Gregory CLEMENT <gregory.clement@free-electrons.com> ---- - drivers/pci/host/pci-mvebu.c | 39 +++++++++++++++++++++++++++++++++++++++ - 1 file changed, 39 insertions(+) - -diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c -index 487c926..008d718 100644 ---- a/drivers/pci/host/pci-mvebu.c -+++ b/drivers/pci/host/pci-mvebu.c -@@ -21,6 +21,7 @@ - #include <linux/of_gpio.h> - #include <linux/of_pci.h> - #include <linux/of_platform.h> -+#include <linux/clk-provider.h> - - /* - * PCIe unit register offsets. -@@ -162,6 +163,14 @@ static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr) - mvebu_writel(port, stat, PCIE_STAT_OFF); - } - -+static u32 mvebu_pcie_get_local_bus_nr(struct mvebu_pcie_port *port) -+{ -+ u32 stat; -+ -+ stat = mvebu_readl(port, PCIE_STAT_OFF); -+ return (stat & PCIE_STAT_BUS) >> 8; -+} -+ - static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr) - { - u32 stat; -@@ -172,6 +181,30 @@ static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr) - mvebu_writel(port, stat, PCIE_STAT_OFF); - } - -+static void mvebu_pcie_wait_dev(struct mvebu_pcie_port *port) -+{ -+ int tries; -+ -+ for (tries = 0; tries < 1000; tries++) { -+ u32 vpid; -+ -+ mvebu_writel(port, -+ PCIE_CONF_ADDR(mvebu_pcie_get_local_bus_nr(port), -+ PCI_DEVFN(0, 0), PCI_VENDOR_ID), -+ PCIE_CONF_ADDR_OFF); -+ vpid = mvebu_readl(port, PCIE_CONF_DATA_OFF); -+ -+ if (vpid != 0xffffffff) -+ break; -+ -+ udelay(100); -+ } -+ -+ if (tries >= 1000) -+ dev_warn(&port->pcie->pdev->dev, -+ "timeout when looking for the PCIe device\n"); -+} -+ - /* - * Setup PCIE BARs and Address Decode Wins: - * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks -@@ -951,6 +984,7 @@ static int mvebu_pcie_probe(struct platform_device *pdev) - for_each_child_of_node(pdev->dev.of_node, child) { - struct mvebu_pcie_port *port = &pcie->ports[i]; - enum of_gpio_flags flags; -+ int linkup; - - if (!of_device_is_available(child)) - continue; -@@ -1035,8 +1069,13 @@ static int mvebu_pcie_probe(struct platform_device *pdev) - continue; - } - -+ linkup = mvebu_pcie_link_up(port); -+ - mvebu_pcie_set_local_dev_nr(port, 1); - -+ if (linkup) -+ mvebu_pcie_wait_dev(port); -+ - port->dn = child; - spin_lock_init(&port->conf_lock); - mvebu_sw_pci_bridge_init(port); --- -1.8.3.2 diff --git a/a/15.hdr b/a/15.hdr deleted file mode 100644 index 8a35205..0000000 --- a/a/15.hdr +++ /dev/null @@ -1,3 +0,0 @@ -Content-Type: text/x-patch -Content-Transfer-Encoding: 7bit -Content-Disposition: attachment; filename=combined.patch diff --git a/a/15.txt b/a/15.txt deleted file mode 100644 index 7072189..0000000 --- a/a/15.txt +++ /dev/null @@ -1,446 +0,0 @@ -diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi -index 74b5964..2188ce6 100644 ---- a/arch/arm/boot/dts/armada-370-xp.dtsi -+++ b/arch/arm/boot/dts/armada-370-xp.dtsi -@@ -44,8 +44,8 @@ - #size-cells = <1>; - controller = <&mbusc>; - interrupt-parent = <&mpic>; -- pcie-mem-aperture = <0xe0000000 0x8000000>; -- pcie-io-aperture = <0xe8000000 0x100000>; -+ pcie-mem-aperture = <0xf8000000 0x7e00000>; -+ pcie-io-aperture = <0xffe00000 0x100000>; - - devbus-bootcs { - compatible = "marvell,mvebu-devbus"; -diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts -index bcf6d79..448373c 100644 ---- a/arch/arm/boot/dts/armada-xp-db.dts -+++ b/arch/arm/boot/dts/armada-xp-db.dts -@@ -2,7 +2,7 @@ - * Device Tree file for Marvell Armada XP evaluation board - * (DB-78460-BP) - * -- * Copyright (C) 2012 Marvell -+ * Copyright (C) 2012-2014 Marvell - * - * Lior Amsalem <alior@marvell.com> - * Gregory CLEMENT <gregory.clement@free-electrons.com> -@@ -11,6 +11,15 @@ - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. -+ * -+ * Note: this Device Tree assumes that the bootloader has remapped the -+ * internal registers to 0xf1000000 (instead of the default -+ * 0xd0000000). The 0xf1000000 is the default used by the recent, -+ * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier -+ * boards were delivered with an older version of the bootloader that -+ * left internal registers mapped at 0xd0000000. If you are in this -+ * situation, you should either update your bootloader (preferred -+ * solution) or the below Device Tree should be adjusted. - */ - - /dts-v1/; -@@ -30,7 +39,7 @@ - }; - - soc { -- ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 -+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 - MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 - MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>; - -diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts -index 274e2ad..61bda68 100644 ---- a/arch/arm/boot/dts/armada-xp-gp.dts -+++ b/arch/arm/boot/dts/armada-xp-gp.dts -@@ -2,7 +2,7 @@ - * Device Tree file for Marvell Armada XP development board - * (DB-MV784MP-GP) - * -- * Copyright (C) 2013 Marvell -+ * Copyright (C) 2013-2014 Marvell - * - * Lior Amsalem <alior@marvell.com> - * Gregory CLEMENT <gregory.clement@free-electrons.com> -@@ -11,6 +11,15 @@ - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. -+ * -+ * Note: this Device Tree assumes that the bootloader has remapped the -+ * internal registers to 0xf1000000 (instead of the default -+ * 0xd0000000). The 0xf1000000 is the default used by the recent, -+ * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier -+ * boards were delivered with an older version of the bootloader that -+ * left internal registers mapped at 0xd0000000. If you are in this -+ * situation, you should either update your bootloader (preferred -+ * solution) or the below Device Tree should be adjusted. - */ - - /dts-v1/; -@@ -30,16 +39,17 @@ - * 8 GB of plug-in RAM modules by default.The amount - * of memory available can be changed by the - * bootloader according the size of the module -- * actually plugged. Only 7GB are usable because -- * addresses from 0xC0000000 to 0xffffffff are used by -- * the internal registers of the SoC. -+ * actually plugged. However, memory between -+ * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is -+ * the address range used for I/O (internal registers, -+ * MBus windows). - */ -- reg = <0x00000000 0x00000000 0x00000000 0xC0000000>, -+ reg = <0x00000000 0x00000000 0x00000000 0xf0000000>, - <0x00000001 0x00000000 0x00000001 0x00000000>; - }; - - soc { -- ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 -+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 - MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 - MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>; - -diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c -index 725c461..54d339e 100644 ---- a/drivers/bus/mvebu-mbus.c -+++ b/drivers/bus/mvebu-mbus.c -@@ -56,6 +56,7 @@ - #include <linux/of.h> - #include <linux/of_address.h> - #include <linux/debugfs.h> -+#include <linux/log2.h> - - /* - * DDR target is the same on all platforms. -@@ -222,12 +223,6 @@ static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus, - */ - if ((u64)base < wend && end > wbase) - return 0; -- -- /* -- * Check if target/attribute conflicts -- */ -- if (target == wtarget && attr == wattr) -- return 0; - } - - return 1; -@@ -266,6 +261,17 @@ static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus, - mbus->soc->win_cfg_offset(win); - u32 ctrl, remap_addr; - -+ if (!is_power_of_2(size)) { -+ WARN(true, "Invalid MBus window size: 0x%zx\n", size); -+ return -EINVAL; -+ } -+ -+ if ((base & (phys_addr_t)(size - 1)) != 0) { -+ WARN(true, "Invalid MBus base/size: %pa len 0x%zx\n", &base, -+ size); -+ return -EINVAL; -+ } -+ - ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) | - (attr << WIN_CTRL_ATTR_SHIFT) | - (target << WIN_CTRL_TGT_SHIFT) | -@@ -413,6 +419,10 @@ static int mvebu_devs_debug_show(struct seq_file *seq, void *v) - win, (unsigned long long)wbase, - (unsigned long long)(wbase + wsize), wtarget, wattr); - -+ if (!is_power_of_2(wsize) || -+ ((wbase & (u64)(wsize - 1)) != 0)) -+ seq_puts(seq, " (Invalid base/size!!)"); -+ - if (win < mbus->soc->num_remappable_wins) { - seq_printf(seq, " (remap %016llx)\n", - (unsigned long long)wremap); -diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c -index 5409564..939eb0d 100644 ---- a/drivers/irqchip/irq-armada-370-xp.c -+++ b/drivers/irqchip/irq-armada-370-xp.c -@@ -130,8 +130,7 @@ static int armada_370_xp_setup_msi_irq(struct msi_chip *chip, - struct msi_desc *desc) - { - struct msi_msg msg; -- irq_hw_number_t hwirq; -- int virq; -+ int virq, hwirq; - - hwirq = armada_370_xp_alloc_msi(); - if (hwirq < 0) -@@ -157,8 +156,19 @@ static void armada_370_xp_teardown_msi_irq(struct msi_chip *chip, - unsigned int irq) - { - struct irq_data *d = irq_get_irq_data(irq); -+ unsigned long hwirq = d->hwirq; -+ - irq_dispose_mapping(irq); -- armada_370_xp_free_msi(d->hwirq); -+ armada_370_xp_free_msi(hwirq); -+} -+ -+static int armada_370_xp_check_msi_device(struct msi_chip *chip, struct pci_dev *dev, -+ int nvec, int type) -+{ -+ /* We support MSI, but not MSI-X */ -+ if (type == PCI_CAP_ID_MSI) -+ return 0; -+ return -EINVAL; - } - - static struct irq_chip armada_370_xp_msi_irq_chip = { -@@ -199,6 +209,7 @@ static int armada_370_xp_msi_init(struct device_node *node, - - msi_chip->setup_irq = armada_370_xp_setup_msi_irq; - msi_chip->teardown_irq = armada_370_xp_teardown_msi_irq; -+ msi_chip->check_device = armada_370_xp_check_msi_device; - msi_chip->of_node = node; - - armada_370_xp_msi_domain = -diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c -index 46d31a4..d9c7eb2 100644 ---- a/drivers/net/ethernet/intel/igb/igb_main.c -+++ b/drivers/net/ethernet/intel/igb/igb_main.c -@@ -1014,6 +1014,12 @@ static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) - { - struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; - -+ /* Coming from igb_set_interrupt_capability, the vectors are not yet -+ * allocated. So, q_vector is NULL so we should stop here. -+ */ -+ if (!q_vector) -+ return; -+ - if (q_vector->tx.ring) - adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; - -@@ -1121,6 +1127,7 @@ static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) - - /* If we can't do MSI-X, try MSI */ - msi_only: -+ adapter->flags &= ~IGB_FLAG_HAS_MSIX; - #ifdef CONFIG_PCI_IOV - /* disable SR-IOV for non MSI-X configurations */ - if (adapter->vf_data) { -diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c -index 0e79665..008d718 100644 ---- a/drivers/pci/host/pci-mvebu.c -+++ b/drivers/pci/host/pci-mvebu.c -@@ -21,6 +21,7 @@ - #include <linux/of_gpio.h> - #include <linux/of_pci.h> - #include <linux/of_platform.h> -+#include <linux/clk-provider.h> - - /* - * PCIe unit register offsets. -@@ -162,6 +163,14 @@ static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr) - mvebu_writel(port, stat, PCIE_STAT_OFF); - } - -+static u32 mvebu_pcie_get_local_bus_nr(struct mvebu_pcie_port *port) -+{ -+ u32 stat; -+ -+ stat = mvebu_readl(port, PCIE_STAT_OFF); -+ return (stat & PCIE_STAT_BUS) >> 8; -+} -+ - static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr) - { - u32 stat; -@@ -172,6 +181,30 @@ static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr) - mvebu_writel(port, stat, PCIE_STAT_OFF); - } - -+static void mvebu_pcie_wait_dev(struct mvebu_pcie_port *port) -+{ -+ int tries; -+ -+ for (tries = 0; tries < 1000; tries++) { -+ u32 vpid; -+ -+ mvebu_writel(port, -+ PCIE_CONF_ADDR(mvebu_pcie_get_local_bus_nr(port), -+ PCI_DEVFN(0, 0), PCI_VENDOR_ID), -+ PCIE_CONF_ADDR_OFF); -+ vpid = mvebu_readl(port, PCIE_CONF_DATA_OFF); -+ -+ if (vpid != 0xffffffff) -+ break; -+ -+ udelay(100); -+ } -+ -+ if (tries >= 1000) -+ dev_warn(&port->pcie->pdev->dev, -+ "timeout when looking for the PCIe device\n"); -+} -+ - /* - * Setup PCIE BARs and Address Decode Wins: - * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks -@@ -291,6 +324,58 @@ static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port, - return PCIBIOS_SUCCESSFUL; - } - -+/* -+ * Remove windows, starting from the largest ones to the smallest -+ * ones. -+ */ -+static void mvebu_pcie_del_windows(struct mvebu_pcie_port *port, -+ phys_addr_t base, size_t size) -+{ -+ while (size) { -+ size_t sz = 1 << (fls(size) - 1); -+ -+ mvebu_mbus_del_window(base, sz); -+ base += sz; -+ size -= sz; -+ } -+} -+ -+/* -+ * MBus windows can only have a power of two size, but PCI BARs do not -+ * have this constraint. Therefore, we have to split the PCI BAR into -+ * areas each having a power of two size. We start from the largest -+ * one (i.e highest order bit set in the size). -+ */ -+static void mvebu_pcie_add_windows(struct mvebu_pcie_port *port, -+ unsigned int target, unsigned int attribute, -+ phys_addr_t base, size_t size, -+ phys_addr_t remap) -+{ -+ size_t size_mapped = 0; -+ -+ while (size) { -+ size_t sz = 1 << (fls(size) - 1); -+ int ret; -+ -+ ret = mvebu_mbus_add_window_remap_by_id(target, attribute, base, -+ sz, remap); -+ if (ret) { -+ dev_err(&port->pcie->pdev->dev, -+ "Could not create MBus window at 0x%x, size 0x%x: %d\n", -+ base, sz, ret); -+ mvebu_pcie_del_windows(port, base - size_mapped, -+ size_mapped); -+ return; -+ } -+ -+ size -= sz; -+ size_mapped += sz; -+ base += sz; -+ if (remap != MVEBU_MBUS_NO_REMAP) -+ remap += sz; -+ } -+} -+ - static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port) - { - phys_addr_t iobase; -@@ -302,8 +387,8 @@ static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port) - - /* If a window was configured, remove it */ - if (port->iowin_base) { -- mvebu_mbus_del_window(port->iowin_base, -- port->iowin_size); -+ mvebu_pcie_del_windows(port, port->iowin_base, -+ port->iowin_size); - port->iowin_base = 0; - port->iowin_size = 0; - } -@@ -329,11 +414,11 @@ static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port) - port->iowin_base = port->pcie->io.start + iobase; - port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) | - (port->bridge.iolimitupper << 16)) - -- iobase); -+ iobase) + 1; - -- mvebu_mbus_add_window_remap_by_id(port->io_target, port->io_attr, -- port->iowin_base, port->iowin_size, -- iobase); -+ mvebu_pcie_add_windows(port, port->io_target, port->io_attr, -+ port->iowin_base, port->iowin_size, -+ iobase); - } - - static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port) -@@ -344,8 +429,8 @@ static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port) - - /* If a window was configured, remove it */ - if (port->memwin_base) { -- mvebu_mbus_del_window(port->memwin_base, -- port->memwin_size); -+ mvebu_pcie_del_windows(port, port->memwin_base, -+ port->memwin_size); - port->memwin_base = 0; - port->memwin_size = 0; - } -@@ -362,10 +447,11 @@ static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port) - port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16); - port->memwin_size = - (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) - -- port->memwin_base; -+ port->memwin_base + 1; - -- mvebu_mbus_add_window_by_id(port->mem_target, port->mem_attr, -- port->memwin_base, port->memwin_size); -+ mvebu_pcie_add_windows(port, port->mem_target, port->mem_attr, -+ port->memwin_base, port->memwin_size, -+ MVEBU_MBUS_NO_REMAP); - } - - /* -@@ -721,14 +807,21 @@ static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev, - - /* - * On the PCI-to-PCI bridge side, the I/O windows must have at -- * least a 64 KB size and be aligned on their size, and the -- * memory windows must have at least a 1 MB size and be -- * aligned on their size -+ * least a 64 KB size and the memory windows must have at -+ * least a 1 MB size. Moreover, MBus windows need to have a -+ * base address aligned on their size, and their size must be -+ * a power of two. This means that if the BAR doesn't have a -+ * power of two size, several MBus windows will actually be -+ * created. We need to ensure that the biggest MBus window -+ * (which will be the first one) is aligned on its size, which -+ * explains the rounddown_pow_of_two() being done here. - */ - if (res->flags & IORESOURCE_IO) -- return round_up(start, max_t(resource_size_t, SZ_64K, size)); -+ return round_up(start, max_t(resource_size_t, SZ_64K, -+ rounddown_pow_of_two(size))); - else if (res->flags & IORESOURCE_MEM) -- return round_up(start, max_t(resource_size_t, SZ_1M, size)); -+ return round_up(start, max_t(resource_size_t, SZ_1M, -+ rounddown_pow_of_two(size))); - else - return start; - } -@@ -891,6 +984,7 @@ static int mvebu_pcie_probe(struct platform_device *pdev) - for_each_child_of_node(pdev->dev.of_node, child) { - struct mvebu_pcie_port *port = &pcie->ports[i]; - enum of_gpio_flags flags; -+ int linkup; - - if (!of_device_is_available(child)) - continue; -@@ -975,8 +1069,13 @@ static int mvebu_pcie_probe(struct platform_device *pdev) - continue; - } - -+ linkup = mvebu_pcie_link_up(port); -+ - mvebu_pcie_set_local_dev_nr(port, 1); - -+ if (linkup) -+ mvebu_pcie_wait_dev(port); -+ - port->dn = child; - spin_lock_init(&port->conf_lock); - mvebu_sw_pci_bridge_init(port); diff --git a/a/2.hdr b/a/2.hdr deleted file mode 100644 index d06192e..0000000 --- a/a/2.hdr +++ /dev/null @@ -1,4 +0,0 @@ -Content-Type: text/x-patch -Content-Transfer-Encoding: 7bit -Content-Disposition: attachment; - filename=0001-igb-Fix-Null-pointer-dereference-in-igb_reset_q_vect.patch diff --git a/a/2.txt b/a/2.txt deleted file mode 100644 index c33cbe2..0000000 --- a/a/2.txt +++ /dev/null @@ -1,45 +0,0 @@ ->From 8996f4001da3d364b3d1b0633e059b5ff3da3b5b Mon Sep 17 00:00:00 2001 -From: Christoph Paasch <christoph.paasch@uclouvain.be> -Date: Fri, 21 Mar 2014 03:48:19 -0700 -Subject: [PATCH 01/13] igb: Fix Null-pointer dereference in igb_reset_q_vector - -When igb_set_interrupt_capability() calls -igb_reset_interrupt_capability() (e.g., because CONFIG_PCI_MSI is unset), -num_q_vectors has been set but no vector has yet been allocated. - -igb_reset_interrupt_capability() will then call igb_reset_q_vector, -which assumes that the vector is allocated. As this is not the case, we -are accessing a NULL-pointer. - -This patch fixes it by checking that q_vector is indeed different from -NULL. - -Fixes: 02ef6e1d0b0023 (igb: Fix queue allocation method to accommodate changing during runtime) -Cc: Carolyn Wyborny <carolyn.wyborny@intel.com> -Signed-off-by: Christoph Paasch <christoph.paasch@uclouvain.be> -Tested-by: Jeff Pieper <jeffrey.e.pieper@intel.com> -Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> -Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> ---- - drivers/net/ethernet/intel/igb/igb_main.c | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c -index 46d31a4..bfcf192 100644 ---- a/drivers/net/ethernet/intel/igb/igb_main.c -+++ b/drivers/net/ethernet/intel/igb/igb_main.c -@@ -1014,6 +1014,12 @@ static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) - { - struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; - -+ /* Coming from igb_set_interrupt_capability, the vectors are not yet -+ * allocated. So, q_vector is NULL so we should stop here. -+ */ -+ if (!q_vector) -+ return; -+ - if (q_vector->tx.ring) - adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; - --- -1.8.3.2 diff --git a/a/3.hdr b/a/3.hdr deleted file mode 100644 index 380c5f3..0000000 --- a/a/3.hdr +++ /dev/null @@ -1,4 +0,0 @@ -Content-Type: text/x-patch -Content-Transfer-Encoding: 7bit -Content-Disposition: attachment; - filename=0002-igb-Unset-IGB_FLAG_HAS_MSIX-flag-when-falling-back-t.patch diff --git a/a/3.txt b/a/3.txt deleted file mode 100644 index 1109d90..0000000 --- a/a/3.txt +++ /dev/null @@ -1,95 +0,0 @@ ->From 9ecd88559e5d53d8923e1942e2a42aa266404554 Mon Sep 17 00:00:00 2001 -From: Christoph Paasch <christoph.paasch@uclouvain.be> -Date: Fri, 21 Mar 2014 04:02:09 -0700 -Subject: [PATCH 02/13] igb: Unset IGB_FLAG_HAS_MSIX-flag when falling back to - msi-only - -Prior to cd14ef54d25 (igb: Change to use statically allocated array for -MSIx entries), having msix_entries different from NULL was an indicator -that MSIX is enabled. -In igb_set_interrupt_capabiliy we may fall back to MSI-only. Prior to -the above patch msix_entries was set to NULL by -igb_reset_interrupt_capability. - -However, now we are checking the flag for IGB_FLAG_HAS_MSIX and so the -stack gets completly confused: - -[ 42.659791] ------------[ cut here ]------------ -[ 42.715032] WARNING: CPU: 7 PID: 0 at net/sched/sch_generic.c:264 dev_watchdog+0x15c/0x1fb() -[ 42.848263] NETDEV WATCHDOG: eth0 (igb): transmit queue 0 timed out -[ 42.923253] Modules linked in: -[ 42.959875] CPU: 7 PID: 0 Comm: swapper/7 Not tainted 3.14.0-rc2-mptcp #437 -[ 43.043184] Hardware name: HP ProLiant DL165 G7, BIOS O37 01/26/2011 -[ 43.119215] 0000000000000108 ffff88023fdc3da8 ffffffff81487847 0000000000000108 -[ 43.208165] ffff88023fdc3df8 ffff88023fdc3de8 ffffffff81034e7d ffff88023fdc3dd8 -[ 43.297120] ffffffff813fff10 ffff880236018000 ffff880236b178c0 0000000000000008 -[ 43.386071] Call Trace: -[ 43.415303] <IRQ> [<ffffffff81487847>] dump_stack+0x49/0x62 -[ 43.484174] [<ffffffff81034e7d>] warn_slowpath_common+0x77/0x91 -[ 43.556049] [<ffffffff813fff10>] ? dev_watchdog+0x15c/0x1fb -[ 43.623759] [<ffffffff81034f2b>] warn_slowpath_fmt+0x41/0x43 -[ 43.692511] [<ffffffff813fff10>] dev_watchdog+0x15c/0x1fb -[ 43.758141] [<ffffffff813ffdb4>] ? __netdev_watchdog_up+0x64/0x64 -[ 43.832091] [<ffffffff8103cd04>] call_timer_fn+0x17/0x6f -[ 43.896682] [<ffffffff8103cebe>] run_timer_softirq+0x162/0x1a2 -[ 43.967511] [<ffffffff81038520>] __do_softirq+0xcd/0x1cc -[ 44.032104] [<ffffffff81038689>] irq_exit+0x3a/0x48 -[ 44.091492] [<ffffffff81026d43>] smp_apic_timer_interrupt+0x43/0x50 -[ 44.167525] [<ffffffff8148c24a>] apic_timer_interrupt+0x6a/0x70 -[ 44.239392] <EOI> [<ffffffff8100992c>] ? default_idle+0x6/0x8 -[ 44.310343] [<ffffffff81009b31>] arch_cpu_idle+0x13/0x18 -[ 44.374934] [<ffffffff81066126>] cpu_startup_entry+0xa7/0x101 -[ 44.444724] [<ffffffff81025660>] start_secondary+0x1b2/0x1b7 -[ 44.513472] ---[ end trace a5a075fd4e7f854f ]--- -[ 44.568753] igb 0000:04:00.0 eth0: Reset adapter -[ 46.206945] random: nonblocking pool is initialized -[ 46.465670] irq 44: nobody cared (try booting with the "irqpoll" option) -[ 46.545862] CPU: 7 PID: 0 Comm: swapper/7 Tainted: G W 3.14.0-rc2-mptcp #437 -[ 46.640610] Hardware name: HP ProLiant DL165 G7, BIOS O37 01/26/2011 -[ 46.716641] ffff8802363f8c84 ffff88023fdc3e38 ffffffff81487847 00000000a03cdb6d -[ 46.805598] ffff8802363f8c00 ffff88023fdc3e68 ffffffff81068489 0000007f81825400 -[ 46.894539] ffff8802363f8c00 0000000000000000 0000000000000000 ffff88023fdc3ea8 -[ 46.983484] Call Trace: -[ 47.012714] <IRQ> [<ffffffff81487847>] dump_stack+0x49/0x62 -[ 47.081585] [<ffffffff81068489>] __report_bad_irq+0x35/0xc1 -[ 47.149295] [<ffffffff81068683>] note_interrupt+0x16e/0x1ea -[ 47.217006] [<ffffffff8106679e>] handle_irq_event_percpu+0x116/0x12e -[ 47.294075] [<ffffffff810667e9>] handle_irq_event+0x33/0x4f -[ 47.361787] [<ffffffff81068c95>] handle_fasteoi_irq+0x83/0xd1 -[ 47.431577] [<ffffffff81003d5b>] handle_irq+0x1f/0x28 -[ 47.493047] [<ffffffff81003567>] do_IRQ+0x4e/0xd4 -[ 47.550358] [<ffffffff8148b06a>] common_interrupt+0x6a/0x6a -[ 47.618066] <EOI> [<ffffffff8100992c>] ? default_idle+0x6/0x8 -[ 47.689016] [<ffffffff81009b31>] arch_cpu_idle+0x13/0x18 -[ 47.753605] [<ffffffff81066126>] cpu_startup_entry+0xa7/0x101 -[ 47.823397] [<ffffffff81025660>] start_secondary+0x1b2/0x1b7 -[ 47.892146] handlers: -[ 47.919301] [<ffffffff812fbd7d>] igb_intr - -So, this patch unsets the flag to indicate that we are not using MSIX. -This patch does exactly this: Unsetting the flag when falling back to MSI. - -Fixes: cd14ef54d25b (igb: Change to use statically allocated array for MSIx entries) -Cc: Carolyn Wyborny <carolyn.wyborny@intel.com> -Signed-off-by: Christoph Paasch <christoph.paasch@uclouvain.be> -Tested-by: Jeff Pieper <jeffrey.e.pieper@intel.com> -Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> -Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> ---- - drivers/net/ethernet/intel/igb/igb_main.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c -index bfcf192..d9c7eb2 100644 ---- a/drivers/net/ethernet/intel/igb/igb_main.c -+++ b/drivers/net/ethernet/intel/igb/igb_main.c -@@ -1127,6 +1127,7 @@ static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) - - /* If we can't do MSI-X, try MSI */ - msi_only: -+ adapter->flags &= ~IGB_FLAG_HAS_MSIX; - #ifdef CONFIG_PCI_IOV - /* disable SR-IOV for non MSI-X configurations */ - if (adapter->vf_data) { --- -1.8.3.2 diff --git a/a/4.hdr b/a/4.hdr deleted file mode 100644 index b9fc4a1..0000000 --- a/a/4.hdr +++ /dev/null @@ -1,4 +0,0 @@ -Content-Type: text/x-patch -Content-Transfer-Encoding: 7bit -Content-Disposition: attachment; - filename=0003-ARM-mvebu-change-the-default-PCIe-apertures-for-Arma.patch diff --git a/a/4.txt b/a/4.txt deleted file mode 100644 index d7bc2c5..0000000 --- a/a/4.txt +++ /dev/null @@ -1,64 +0,0 @@ ->From dc1e59a9dddf9f39b9a68fdd6d75e4517811de3b Mon Sep 17 00:00:00 2001 -From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> -Date: Tue, 4 Mar 2014 17:36:59 +0100 -Subject: [PATCH 03/13] ARM: mvebu: change the default PCIe apertures for - Armada 370/XP - -The latest Marvell bootloaders for various boards change the MBus -Window base address from 0xC0000000 to 0xF0000000, in order to make -more RAM in the first 4 GB actually usable by the kernel (RAM that is -covered by the MBus window is "shadowed" and therefore not usable). - -However, our default PCIe memory and I/O apertures where sitting at -0xe0000000 (for memory) and 0xe8000000 (for I/O), which will now be -outside of the MBus Window range on those platforms. To make things -work, we have to ensure those apertures use addresses in the -0xF0000000 -> 0xFFFFFFFF range. - -Of course this change of the MBus Window base address from 0xC0000000 -to 0xF0000000 also comes with a change of the internal register base -address from 0xD0000000 to 0xF1000000. - -We have therefore designed the following memory map: - - * 0xF0000000 -> 0xF1000000: 16 MB, used for NOR flashes on Armada XP - GP and Armada XP DB. - - * 0xF1000000 -> 0xF1100000: 1 MB, used for internal registers. - - * 0xF8000000 -> 0xFFE00000: 126 MB, used for PCIe memory. - - * 0xFFE00000 -> 0xFFF00000: 1 MB, used for PCIe I/O. - - * 0xFFF00000 -> 0xFFFFFFFF: 1 MB, used for the BootROM mapping - -There is one exception to this layout: the Armada XP OpenBlocks, which -has a 128 MB NOR flash, mapped from 0xF0000000 to 0xF8000000. This -does not conflict with the current change for the PCIe I/O and memory -apertures, and continues to work because on Armada XP OpenBlocks, the -bootloader is an old one, and continues to have internal registers -mapped at 0xD0000000. - -Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> -Signed-off-by: Jason Cooper <jason@lakedaemon.net> ---- - arch/arm/boot/dts/armada-370-xp.dtsi | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi -index 74b5964..2188ce6 100644 ---- a/arch/arm/boot/dts/armada-370-xp.dtsi -+++ b/arch/arm/boot/dts/armada-370-xp.dtsi -@@ -44,8 +44,8 @@ - #size-cells = <1>; - controller = <&mbusc>; - interrupt-parent = <&mpic>; -- pcie-mem-aperture = <0xe0000000 0x8000000>; -- pcie-io-aperture = <0xe8000000 0x100000>; -+ pcie-mem-aperture = <0xf8000000 0x7e00000>; -+ pcie-io-aperture = <0xffe00000 0x100000>; - - devbus-bootcs { - compatible = "marvell,mvebu-devbus"; --- -1.8.3.2 diff --git a/a/5.hdr b/a/5.hdr deleted file mode 100644 index 38efd09..0000000 --- a/a/5.hdr +++ /dev/null @@ -1,4 +0,0 @@ -Content-Type: text/x-patch -Content-Transfer-Encoding: 7bit -Content-Disposition: attachment; - filename=0004-ARM-mvebu-switch-the-Armada-XP-DB-to-use-internal-re.patch diff --git a/a/5.txt b/a/5.txt deleted file mode 100644 index effed75..0000000 --- a/a/5.txt +++ /dev/null @@ -1,63 +0,0 @@ ->From b6ee050ba68e679ffc4549cb13913ba643c52d83 Mon Sep 17 00:00:00 2001 -From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> -Date: Tue, 4 Mar 2014 17:37:00 +0100 -Subject: [PATCH 04/13] ARM: mvebu: switch the Armada XP DB to use internal - registers at 0xf1000000 - -Marvell has now provided bootloaders that are Device Tree capable for -the Armada XP DB board, and that also remap the internal register base -address to 0xf1000000. In addition, the bootloader now sets the MBus -Window base address to 0xf0000000, but on this board, this change -doesn't make much difference since the board is by default equipped -with 2 GB of RAM. - -Therefore this commit updates the soc->ranges Device Tree property -with the fact that the internal registers are now mapped at -0xf1000000. - -Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> -Signed-off-by: Jason Cooper <jason@lakedaemon.net> ---- - arch/arm/boot/dts/armada-xp-db.dts | 13 +++++++++++-- - 1 file changed, 11 insertions(+), 2 deletions(-) - -diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts -index bcf6d79..448373c 100644 ---- a/arch/arm/boot/dts/armada-xp-db.dts -+++ b/arch/arm/boot/dts/armada-xp-db.dts -@@ -2,7 +2,7 @@ - * Device Tree file for Marvell Armada XP evaluation board - * (DB-78460-BP) - * -- * Copyright (C) 2012 Marvell -+ * Copyright (C) 2012-2014 Marvell - * - * Lior Amsalem <alior@marvell.com> - * Gregory CLEMENT <gregory.clement@free-electrons.com> -@@ -11,6 +11,15 @@ - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. -+ * -+ * Note: this Device Tree assumes that the bootloader has remapped the -+ * internal registers to 0xf1000000 (instead of the default -+ * 0xd0000000). The 0xf1000000 is the default used by the recent, -+ * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier -+ * boards were delivered with an older version of the bootloader that -+ * left internal registers mapped at 0xd0000000. If you are in this -+ * situation, you should either update your bootloader (preferred -+ * solution) or the below Device Tree should be adjusted. - */ - - /dts-v1/; -@@ -30,7 +39,7 @@ - }; - - soc { -- ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 -+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 - MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 - MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>; - --- -1.8.3.2 diff --git a/a/6.hdr b/a/6.hdr deleted file mode 100644 index 5d83a67..0000000 --- a/a/6.hdr +++ /dev/null @@ -1,4 +0,0 @@ -Content-Type: text/x-patch -Content-Transfer-Encoding: 7bit -Content-Disposition: attachment; - filename=0005-ARM-mvebu-switch-the-Armada-XP-GP-to-use-internal-re.patch diff --git a/a/6.txt b/a/6.txt deleted file mode 100644 index bc922d4..0000000 --- a/a/6.txt +++ /dev/null @@ -1,82 +0,0 @@ ->From 05124e6a87b68c1aa1d138d1b1c0662386b9eab6 Mon Sep 17 00:00:00 2001 -From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> -Date: Tue, 4 Mar 2014 17:37:01 +0100 -Subject: [PATCH 05/13] ARM: mvebu: switch the Armada XP GP to use internal - registers at 0xf1000000 - -Marvell has now provided bootloaders that are Device Tree capable for -the Armada XP GP board, and that also remap the internal register base -address to 0xf1000000. In addition, the bootloader now sets the MBus -Window base address to 0xf0000000, which allows to use much more RAM -in the last GB of RAM before the 4 GB limit (the entire space from -0xC0000000 to 0xFFFFFFFF was not usable due to being used for I/O, not -only the space from 0xF0000000 to 0xFFFFFFFF is used for I/O). - -Therefore this commit: - - * Updates the memory->reg Device Tree property with the fact that in - the first bank of RAM, memory up to 0xf0000000 can be used. - - * Updates the soc->ranges Device Tree property with the fact that the - internal registers are now mapped at 0xf1000000. - -Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> -Signed-off-by: Jason Cooper <jason@lakedaemon.net> ---- - arch/arm/boot/dts/armada-xp-gp.dts | 22 ++++++++++++++++------ - 1 file changed, 16 insertions(+), 6 deletions(-) - -diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts -index 274e2ad..61bda68 100644 ---- a/arch/arm/boot/dts/armada-xp-gp.dts -+++ b/arch/arm/boot/dts/armada-xp-gp.dts -@@ -2,7 +2,7 @@ - * Device Tree file for Marvell Armada XP development board - * (DB-MV784MP-GP) - * -- * Copyright (C) 2013 Marvell -+ * Copyright (C) 2013-2014 Marvell - * - * Lior Amsalem <alior@marvell.com> - * Gregory CLEMENT <gregory.clement@free-electrons.com> -@@ -11,6 +11,15 @@ - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. -+ * -+ * Note: this Device Tree assumes that the bootloader has remapped the -+ * internal registers to 0xf1000000 (instead of the default -+ * 0xd0000000). The 0xf1000000 is the default used by the recent, -+ * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier -+ * boards were delivered with an older version of the bootloader that -+ * left internal registers mapped at 0xd0000000. If you are in this -+ * situation, you should either update your bootloader (preferred -+ * solution) or the below Device Tree should be adjusted. - */ - - /dts-v1/; -@@ -30,16 +39,17 @@ - * 8 GB of plug-in RAM modules by default.The amount - * of memory available can be changed by the - * bootloader according the size of the module -- * actually plugged. Only 7GB are usable because -- * addresses from 0xC0000000 to 0xffffffff are used by -- * the internal registers of the SoC. -+ * actually plugged. However, memory between -+ * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is -+ * the address range used for I/O (internal registers, -+ * MBus windows). - */ -- reg = <0x00000000 0x00000000 0x00000000 0xC0000000>, -+ reg = <0x00000000 0x00000000 0x00000000 0xf0000000>, - <0x00000001 0x00000000 0x00000001 0x00000000>; - }; - - soc { -- ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 -+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 - MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 - MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>; - --- -1.8.3.2 diff --git a/a/7.hdr b/a/7.hdr deleted file mode 100644 index 995d8de..0000000 --- a/a/7.hdr +++ /dev/null @@ -1,4 +0,0 @@ -Content-Type: text/x-patch -Content-Transfer-Encoding: 7bit -Content-Disposition: attachment; - filename=0006-irqchip-armada-370-xp-fix-invalid-cast-of-signed-val.patch diff --git a/a/7.txt b/a/7.txt deleted file mode 100644 index f7e2bf6..0000000 --- a/a/7.txt +++ /dev/null @@ -1,37 +0,0 @@ ->From 5881c7df1167750b103a3612876c0d1c37b55345 Mon Sep 17 00:00:00 2001 -From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> -Date: Tue, 8 Apr 2014 17:33:31 +0200 -Subject: [PATCH 06/13] irqchip: armada-370-xp: fix invalid cast of signed - value into unsigned variable - -The armada_370_xp_alloc_msi() function returns a signed int, which is -negative on error. However, we store the return value into an -irq_hw_number_t, which is unsigned. Therefore, we actually never test -if armada_370_xp_alloc_msi() returns an error or not, which may lead -us to use hwirq numbers of as 0xffffffe4 (when -armada_370_xp_alloc_msi() returns -ENOSPC). - -This commit fixes that by storing the return value of -armada_370_xp_alloc_msi() in a signed variable. - -Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> ---- - drivers/irqchip/irq-armada-370-xp.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - -diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c -index 5409564..7858729 100644 ---- a/drivers/irqchip/irq-armada-370-xp.c -+++ b/drivers/irqchip/irq-armada-370-xp.c -@@ -130,8 +130,7 @@ static int armada_370_xp_setup_msi_irq(struct msi_chip *chip, - struct msi_desc *desc) - { - struct msi_msg msg; -- irq_hw_number_t hwirq; -- int virq; -+ int virq, hwirq; - - hwirq = armada_370_xp_alloc_msi(); - if (hwirq < 0) --- -1.8.3.2 diff --git a/a/8.hdr b/a/8.hdr deleted file mode 100644 index 6f8133e..0000000 --- a/a/8.hdr +++ /dev/null @@ -1,4 +0,0 @@ -Content-Type: text/x-patch -Content-Transfer-Encoding: 7bit -Content-Disposition: attachment; - filename=0007-irqchip-armada-370-xp-implement-the-check_device-msi.patch diff --git a/a/8.txt b/a/8.txt deleted file mode 100644 index 75ae633..0000000 --- a/a/8.txt +++ /dev/null @@ -1,46 +0,0 @@ ->From 8ee3f1764fdc1c49b4199b36d21e5f40f53eca4f Mon Sep 17 00:00:00 2001 -From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> -Date: Tue, 8 Apr 2014 17:35:23 +0200 -Subject: [PATCH 07/13] irqchip: armada-370-xp: implement the ->check_device() - msi_chip operation - -Until now, we were leaving the ->check_device() msi_chip operation -empty, which leads the PCI core to believe that we support both MSI -and MSI-X. In fact, we do not support MSI-X, so we have to tell this -to the PCI core by providing an implementation of this operation. - -Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> ---- - drivers/irqchip/irq-armada-370-xp.c | 10 ++++++++++ - 1 file changed, 10 insertions(+) - -diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c -index 7858729..5d925af 100644 ---- a/drivers/irqchip/irq-armada-370-xp.c -+++ b/drivers/irqchip/irq-armada-370-xp.c -@@ -160,6 +160,15 @@ static void armada_370_xp_teardown_msi_irq(struct msi_chip *chip, - armada_370_xp_free_msi(d->hwirq); - } - -+static int armada_370_xp_check_msi_device(struct msi_chip *chip, struct pci_dev *dev, -+ int nvec, int type) -+{ -+ /* We support MSI, but not MSI-X */ -+ if (type == PCI_CAP_ID_MSI) -+ return 0; -+ return -EINVAL; -+} -+ - static struct irq_chip armada_370_xp_msi_irq_chip = { - .name = "armada_370_xp_msi_irq", - .irq_enable = unmask_msi_irq, -@@ -198,6 +207,7 @@ static int armada_370_xp_msi_init(struct device_node *node, - - msi_chip->setup_irq = armada_370_xp_setup_msi_irq; - msi_chip->teardown_irq = armada_370_xp_teardown_msi_irq; -+ msi_chip->check_device = armada_370_xp_check_msi_device; - msi_chip->of_node = node; - - armada_370_xp_msi_domain = --- -1.8.3.2 diff --git a/a/9.hdr b/a/9.hdr deleted file mode 100644 index a26793c..0000000 --- a/a/9.hdr +++ /dev/null @@ -1,4 +0,0 @@ -Content-Type: text/x-patch -Content-Transfer-Encoding: 7bit -Content-Disposition: attachment; - filename=0008-irqchip-armada-370-xp-Fix-releasing-of-MSIs.patch diff --git a/a/9.txt b/a/9.txt deleted file mode 100644 index 147fb22..0000000 --- a/a/9.txt +++ /dev/null @@ -1,33 +0,0 @@ ->From 3521e42c3b6880fc466ef431e766d71bf77b206e Mon Sep 17 00:00:00 2001 -From: Neil Greatorex <neil@fatboyfat.co.uk> -Date: Sun, 6 Apr 2014 16:10:43 +0100 -Subject: [PATCH 08/13] irqchip: armada-370-xp: Fix releasing of MSIs - -Store the value of d->hwirq in a local variable as the real value is wiped out -by calling irq_dispose_mapping. Without this patch, the armada_370_xp_free_msi -function would always free MSI#0, no matter what was passed to it. - -Signed-off-by: Neil Greatorex <neil@fatboyfat.co.uk> -Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> ---- - drivers/irqchip/irq-armada-370-xp.c | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c -index 5d925af..939eb0d 100644 ---- a/drivers/irqchip/irq-armada-370-xp.c -+++ b/drivers/irqchip/irq-armada-370-xp.c -@@ -156,8 +156,10 @@ static void armada_370_xp_teardown_msi_irq(struct msi_chip *chip, - unsigned int irq) - { - struct irq_data *d = irq_get_irq_data(irq); -+ unsigned long hwirq = d->hwirq; -+ - irq_dispose_mapping(irq); -- armada_370_xp_free_msi(d->hwirq); -+ armada_370_xp_free_msi(hwirq); - } - - static int armada_370_xp_check_msi_device(struct msi_chip *chip, struct pci_dev *dev, --- -1.8.3.2 diff --git a/a/content_digest b/N1/content_digest index c977eeb..85427da 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,21 +1,9 @@ "ref\020140410181953.50ccfcc3@skate\0" - "From\0Thomas Petazzoni <thomas.petazzoni@free-electrons.com>\0" - "Subject\0Re: Fixing PCIe issues on Armada XP\0" + "From\0thomas.petazzoni@free-electrons.com (Thomas Petazzoni)\0" + "Subject\0Fixing PCIe issues on Armada XP\0" "Date\0Fri, 11 Apr 2014 16:32:28 +0200\0" - "To\0Jason Gunthorpe <jgunthorpe@obsidianresearch.com>" - Neil Greatorex <neil@fatboyfat.co.uk> - Willy Tarreau <w@1wt.eu> - Matthew Minter <matthew_minter@xyratex.com> - " Gerlando Falauto <gerlando.falauto@keymile.com>\0" - "Cc\0Lior Amsalem <alior@marvell.com>" - Andrew Lunn <andrew@lunn.ch> - Jason Cooper <jason@lakedaemon.net> - Tawfik Bayouk <tawfik@marvell.com> - linux-pci@vger.kernel.org - Ezequiel Garcia <ezequiel.garcia@free-electrons.com> - " Gregory Cl\303\251ment <gregory.clement@free-electrons.com>" - " linux-arm-kernel@lists.infradead.org\0" - "\01:1\0" + "To\0linux-arm-kernel@lists.infradead.org\0" + "\00:1\0" "b\0" "Hello all,\n" "\n" @@ -57,1389 +45,104 @@ "-- \n" "Thomas Petazzoni, CTO, Free Electrons\n" "Embedded Linux, Kernel and Android engineering\n" - http://free-electrons.com - "\01:2\0" - "fn\00001-igb-Fix-Null-pointer-dereference-in-igb_reset_q_vect.patch\0" - "b\0" - ">From 8996f4001da3d364b3d1b0633e059b5ff3da3b5b Mon Sep 17 00:00:00 2001\n" - "From: Christoph Paasch <christoph.paasch@uclouvain.be>\n" - "Date: Fri, 21 Mar 2014 03:48:19 -0700\n" - "Subject: [PATCH 01/13] igb: Fix Null-pointer dereference in igb_reset_q_vector\n" - "\n" - "When igb_set_interrupt_capability() calls\n" - "igb_reset_interrupt_capability() (e.g., because CONFIG_PCI_MSI is unset),\n" - "num_q_vectors has been set but no vector has yet been allocated.\n" - "\n" - "igb_reset_interrupt_capability() will then call igb_reset_q_vector,\n" - "which assumes that the vector is allocated. As this is not the case, we\n" - "are accessing a NULL-pointer.\n" - "\n" - "This patch fixes it by checking that q_vector is indeed different from\n" - "NULL.\n" - "\n" - "Fixes: 02ef6e1d0b0023 (igb: Fix queue allocation method to accommodate changing during runtime)\n" - "Cc: Carolyn Wyborny <carolyn.wyborny@intel.com>\n" - "Signed-off-by: Christoph Paasch <christoph.paasch@uclouvain.be>\n" - "Tested-by: Jeff Pieper <jeffrey.e.pieper@intel.com>\n" - "Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>\n" - "Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>\n" - "---\n" - " drivers/net/ethernet/intel/igb/igb_main.c | 6 ++++++\n" - " 1 file changed, 6 insertions(+)\n" - "\n" - "diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c\n" - "index 46d31a4..bfcf192 100644\n" - "--- a/drivers/net/ethernet/intel/igb/igb_main.c\n" - "+++ b/drivers/net/ethernet/intel/igb/igb_main.c\n" - "@@ -1014,6 +1014,12 @@ static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)\n" - " {\n" - " \tstruct igb_q_vector *q_vector = adapter->q_vector[v_idx];\n" - " \n" - "+\t/* Coming from igb_set_interrupt_capability, the vectors are not yet\n" - "+\t * allocated. So, q_vector is NULL so we should stop here.\n" - "+\t */\n" - "+\tif (!q_vector)\n" - "+\t\treturn;\n" - "+\n" - " \tif (q_vector->tx.ring)\n" - " \t\tadapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;\n" - " \n" - "-- \n" - 1.8.3.2 - "\01:3\0" - "fn\00002-igb-Unset-IGB_FLAG_HAS_MSIX-flag-when-falling-back-t.patch\0" - "b\0" - ">From 9ecd88559e5d53d8923e1942e2a42aa266404554 Mon Sep 17 00:00:00 2001\n" - "From: Christoph Paasch <christoph.paasch@uclouvain.be>\n" - "Date: Fri, 21 Mar 2014 04:02:09 -0700\n" - "Subject: [PATCH 02/13] igb: Unset IGB_FLAG_HAS_MSIX-flag when falling back to\n" - " msi-only\n" - "\n" - "Prior to cd14ef54d25 (igb: Change to use statically allocated array for\n" - "MSIx entries), having msix_entries different from NULL was an indicator\n" - "that MSIX is enabled.\n" - "In igb_set_interrupt_capabiliy we may fall back to MSI-only. Prior to\n" - "the above patch msix_entries was set to NULL by\n" - "igb_reset_interrupt_capability.\n" - "\n" - "However, now we are checking the flag for IGB_FLAG_HAS_MSIX and so the\n" - "stack gets completly confused:\n" - "\n" - "[ 42.659791] ------------[ cut here ]------------\n" - "[ 42.715032] WARNING: CPU: 7 PID: 0 at net/sched/sch_generic.c:264 dev_watchdog+0x15c/0x1fb()\n" - "[ 42.848263] NETDEV WATCHDOG: eth0 (igb): transmit queue 0 timed out\n" - "[ 42.923253] Modules linked in:\n" - "[ 42.959875] CPU: 7 PID: 0 Comm: swapper/7 Not tainted 3.14.0-rc2-mptcp #437\n" - "[ 43.043184] Hardware name: HP ProLiant DL165 G7, BIOS O37 01/26/2011\n" - "[ 43.119215] 0000000000000108 ffff88023fdc3da8 ffffffff81487847 0000000000000108\n" - "[ 43.208165] ffff88023fdc3df8 ffff88023fdc3de8 ffffffff81034e7d ffff88023fdc3dd8\n" - "[ 43.297120] ffffffff813fff10 ffff880236018000 ffff880236b178c0 0000000000000008\n" - "[ 43.386071] Call Trace:\n" - "[ 43.415303] <IRQ> [<ffffffff81487847>] dump_stack+0x49/0x62\n" - "[ 43.484174] [<ffffffff81034e7d>] warn_slowpath_common+0x77/0x91\n" - "[ 43.556049] [<ffffffff813fff10>] ? dev_watchdog+0x15c/0x1fb\n" - "[ 43.623759] [<ffffffff81034f2b>] warn_slowpath_fmt+0x41/0x43\n" - "[ 43.692511] [<ffffffff813fff10>] dev_watchdog+0x15c/0x1fb\n" - "[ 43.758141] [<ffffffff813ffdb4>] ? __netdev_watchdog_up+0x64/0x64\n" - "[ 43.832091] [<ffffffff8103cd04>] call_timer_fn+0x17/0x6f\n" - "[ 43.896682] [<ffffffff8103cebe>] run_timer_softirq+0x162/0x1a2\n" - "[ 43.967511] [<ffffffff81038520>] __do_softirq+0xcd/0x1cc\n" - "[ 44.032104] [<ffffffff81038689>] irq_exit+0x3a/0x48\n" - "[ 44.091492] [<ffffffff81026d43>] smp_apic_timer_interrupt+0x43/0x50\n" - "[ 44.167525] [<ffffffff8148c24a>] apic_timer_interrupt+0x6a/0x70\n" - "[ 44.239392] <EOI> [<ffffffff8100992c>] ? default_idle+0x6/0x8\n" - "[ 44.310343] [<ffffffff81009b31>] arch_cpu_idle+0x13/0x18\n" - "[ 44.374934] [<ffffffff81066126>] cpu_startup_entry+0xa7/0x101\n" - "[ 44.444724] [<ffffffff81025660>] start_secondary+0x1b2/0x1b7\n" - "[ 44.513472] ---[ end trace a5a075fd4e7f854f ]---\n" - "[ 44.568753] igb 0000:04:00.0 eth0: Reset adapter\n" - "[ 46.206945] random: nonblocking pool is initialized\n" - "[ 46.465670] irq 44: nobody cared (try booting with the \"irqpoll\" option)\n" - "[ 46.545862] CPU: 7 PID: 0 Comm: swapper/7 Tainted: G W 3.14.0-rc2-mptcp #437\n" - "[ 46.640610] Hardware name: HP ProLiant DL165 G7, BIOS O37 01/26/2011\n" - "[ 46.716641] ffff8802363f8c84 ffff88023fdc3e38 ffffffff81487847 00000000a03cdb6d\n" - "[ 46.805598] ffff8802363f8c00 ffff88023fdc3e68 ffffffff81068489 0000007f81825400\n" - "[ 46.894539] ffff8802363f8c00 0000000000000000 0000000000000000 ffff88023fdc3ea8\n" - "[ 46.983484] Call Trace:\n" - "[ 47.012714] <IRQ> [<ffffffff81487847>] dump_stack+0x49/0x62\n" - "[ 47.081585] [<ffffffff81068489>] __report_bad_irq+0x35/0xc1\n" - "[ 47.149295] [<ffffffff81068683>] note_interrupt+0x16e/0x1ea\n" - "[ 47.217006] [<ffffffff8106679e>] handle_irq_event_percpu+0x116/0x12e\n" - "[ 47.294075] [<ffffffff810667e9>] handle_irq_event+0x33/0x4f\n" - "[ 47.361787] [<ffffffff81068c95>] handle_fasteoi_irq+0x83/0xd1\n" - "[ 47.431577] [<ffffffff81003d5b>] handle_irq+0x1f/0x28\n" - "[ 47.493047] [<ffffffff81003567>] do_IRQ+0x4e/0xd4\n" - "[ 47.550358] [<ffffffff8148b06a>] common_interrupt+0x6a/0x6a\n" - "[ 47.618066] <EOI> [<ffffffff8100992c>] ? default_idle+0x6/0x8\n" - "[ 47.689016] [<ffffffff81009b31>] arch_cpu_idle+0x13/0x18\n" - "[ 47.753605] [<ffffffff81066126>] cpu_startup_entry+0xa7/0x101\n" - "[ 47.823397] [<ffffffff81025660>] start_secondary+0x1b2/0x1b7\n" - "[ 47.892146] handlers:\n" - "[ 47.919301] [<ffffffff812fbd7d>] igb_intr\n" - "\n" - "So, this patch unsets the flag to indicate that we are not using MSIX.\n" - "This patch does exactly this: Unsetting the flag when falling back to MSI.\n" - "\n" - "Fixes: cd14ef54d25b (igb: Change to use statically allocated array for MSIx entries)\n" - "Cc: Carolyn Wyborny <carolyn.wyborny@intel.com>\n" - "Signed-off-by: Christoph Paasch <christoph.paasch@uclouvain.be>\n" - "Tested-by: Jeff Pieper <jeffrey.e.pieper@intel.com>\n" - "Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>\n" - "Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>\n" - "---\n" - " drivers/net/ethernet/intel/igb/igb_main.c | 1 +\n" - " 1 file changed, 1 insertion(+)\n" - "\n" - "diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c\n" - "index bfcf192..d9c7eb2 100644\n" - "--- a/drivers/net/ethernet/intel/igb/igb_main.c\n" - "+++ b/drivers/net/ethernet/intel/igb/igb_main.c\n" - "@@ -1127,6 +1127,7 @@ static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)\n" - " \n" - " \t/* If we can't do MSI-X, try MSI */\n" - " msi_only:\n" - "+\tadapter->flags &= ~IGB_FLAG_HAS_MSIX;\n" - " #ifdef CONFIG_PCI_IOV\n" - " \t/* disable SR-IOV for non MSI-X configurations */\n" - " \tif (adapter->vf_data) {\n" - "-- \n" - 1.8.3.2 - "\01:4\0" - "fn\00003-ARM-mvebu-change-the-default-PCIe-apertures-for-Arma.patch\0" - "b\0" - ">From dc1e59a9dddf9f39b9a68fdd6d75e4517811de3b Mon Sep 17 00:00:00 2001\n" - "From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>\n" - "Date: Tue, 4 Mar 2014 17:36:59 +0100\n" - "Subject: [PATCH 03/13] ARM: mvebu: change the default PCIe apertures for\n" - " Armada 370/XP\n" - "\n" - "The latest Marvell bootloaders for various boards change the MBus\n" - "Window base address from 0xC0000000 to 0xF0000000, in order to make\n" - "more RAM in the first 4 GB actually usable by the kernel (RAM that is\n" - "covered by the MBus window is \"shadowed\" and therefore not usable).\n" - "\n" - "However, our default PCIe memory and I/O apertures where sitting at\n" - "0xe0000000 (for memory) and 0xe8000000 (for I/O), which will now be\n" - "outside of the MBus Window range on those platforms. To make things\n" - "work, we have to ensure those apertures use addresses in the\n" - "0xF0000000 -> 0xFFFFFFFF range.\n" - "\n" - "Of course this change of the MBus Window base address from 0xC0000000\n" - "to 0xF0000000 also comes with a change of the internal register base\n" - "address from 0xD0000000 to 0xF1000000.\n" - "\n" - "We have therefore designed the following memory map:\n" - "\n" - " * 0xF0000000 -> 0xF1000000: 16 MB, used for NOR flashes on Armada XP\n" - " GP and Armada XP DB.\n" - "\n" - " * 0xF1000000 -> 0xF1100000: 1 MB, used for internal registers.\n" - "\n" - " * 0xF8000000 -> 0xFFE00000: 126 MB, used for PCIe memory.\n" - "\n" - " * 0xFFE00000 -> 0xFFF00000: 1 MB, used for PCIe I/O.\n" - "\n" - " * 0xFFF00000 -> 0xFFFFFFFF: 1 MB, used for the BootROM mapping\n" - "\n" - "There is one exception to this layout: the Armada XP OpenBlocks, which\n" - "has a 128 MB NOR flash, mapped from 0xF0000000 to 0xF8000000. This\n" - "does not conflict with the current change for the PCIe I/O and memory\n" - "apertures, and continues to work because on Armada XP OpenBlocks, the\n" - "bootloader is an old one, and continues to have internal registers\n" - "mapped at 0xD0000000.\n" - "\n" - "Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>\n" - "Signed-off-by: Jason Cooper <jason@lakedaemon.net>\n" - "---\n" - " arch/arm/boot/dts/armada-370-xp.dtsi | 4 ++--\n" - " 1 file changed, 2 insertions(+), 2 deletions(-)\n" - "\n" - "diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi\n" - "index 74b5964..2188ce6 100644\n" - "--- a/arch/arm/boot/dts/armada-370-xp.dtsi\n" - "+++ b/arch/arm/boot/dts/armada-370-xp.dtsi\n" - "@@ -44,8 +44,8 @@\n" - " \t\t#size-cells = <1>;\n" - " \t\tcontroller = <&mbusc>;\n" - " \t\tinterrupt-parent = <&mpic>;\n" - "-\t\tpcie-mem-aperture = <0xe0000000 0x8000000>;\n" - "-\t\tpcie-io-aperture = <0xe8000000 0x100000>;\n" - "+\t\tpcie-mem-aperture = <0xf8000000 0x7e00000>;\n" - "+\t\tpcie-io-aperture = <0xffe00000 0x100000>;\n" - " \n" - " \t\tdevbus-bootcs {\n" - " \t\t\tcompatible = \"marvell,mvebu-devbus\";\n" - "-- \n" - 1.8.3.2 - "\01:5\0" - "fn\00004-ARM-mvebu-switch-the-Armada-XP-DB-to-use-internal-re.patch\0" - "b\0" - ">From b6ee050ba68e679ffc4549cb13913ba643c52d83 Mon Sep 17 00:00:00 2001\n" - "From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>\n" - "Date: Tue, 4 Mar 2014 17:37:00 +0100\n" - "Subject: [PATCH 04/13] ARM: mvebu: switch the Armada XP DB to use internal\n" - " registers at 0xf1000000\n" - "\n" - "Marvell has now provided bootloaders that are Device Tree capable for\n" - "the Armada XP DB board, and that also remap the internal register base\n" - "address to 0xf1000000. In addition, the bootloader now sets the MBus\n" - "Window base address to 0xf0000000, but on this board, this change\n" - "doesn't make much difference since the board is by default equipped\n" - "with 2 GB of RAM.\n" - "\n" - "Therefore this commit updates the soc->ranges Device Tree property\n" - "with the fact that the internal registers are now mapped at\n" - "0xf1000000.\n" - "\n" - "Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>\n" - "Signed-off-by: Jason Cooper <jason@lakedaemon.net>\n" - "---\n" - " arch/arm/boot/dts/armada-xp-db.dts | 13 +++++++++++--\n" - " 1 file changed, 11 insertions(+), 2 deletions(-)\n" - "\n" - "diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts\n" - "index bcf6d79..448373c 100644\n" - "--- a/arch/arm/boot/dts/armada-xp-db.dts\n" - "+++ b/arch/arm/boot/dts/armada-xp-db.dts\n" - "@@ -2,7 +2,7 @@\n" - " * Device Tree file for Marvell Armada XP evaluation board\n" - " * (DB-78460-BP)\n" - " *\n" - "- * Copyright (C) 2012 Marvell\n" - "+ * Copyright (C) 2012-2014 Marvell\n" - " *\n" - " * Lior Amsalem <alior@marvell.com>\n" - " * Gregory CLEMENT <gregory.clement@free-electrons.com>\n" - "@@ -11,6 +11,15 @@\n" - " * This file is licensed under the terms of the GNU General Public\n" - " * License version 2. This program is licensed \"as is\" without any\n" - " * warranty of any kind, whether express or implied.\n" - "+ *\n" - "+ * Note: this Device Tree assumes that the bootloader has remapped the\n" - "+ * internal registers to 0xf1000000 (instead of the default\n" - "+ * 0xd0000000). The 0xf1000000 is the default used by the recent,\n" - "+ * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier\n" - "+ * boards were delivered with an older version of the bootloader that\n" - "+ * left internal registers mapped at 0xd0000000. If you are in this\n" - "+ * situation, you should either update your bootloader (preferred\n" - "+ * solution) or the below Device Tree should be adjusted.\n" - " */\n" - " \n" - " /dts-v1/;\n" - "@@ -30,7 +39,7 @@\n" - " \t};\n" - " \n" - " \tsoc {\n" - "-\t\tranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000\n" - "+\t\tranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000\n" - " \t\t\t MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000\n" - " \t\t\t MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;\n" - " \n" - "-- \n" - 1.8.3.2 - "\01:6\0" - "fn\00005-ARM-mvebu-switch-the-Armada-XP-GP-to-use-internal-re.patch\0" - "b\0" - ">From 05124e6a87b68c1aa1d138d1b1c0662386b9eab6 Mon Sep 17 00:00:00 2001\n" - "From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>\n" - "Date: Tue, 4 Mar 2014 17:37:01 +0100\n" - "Subject: [PATCH 05/13] ARM: mvebu: switch the Armada XP GP to use internal\n" - " registers at 0xf1000000\n" - "\n" - "Marvell has now provided bootloaders that are Device Tree capable for\n" - "the Armada XP GP board, and that also remap the internal register base\n" - "address to 0xf1000000. In addition, the bootloader now sets the MBus\n" - "Window base address to 0xf0000000, which allows to use much more RAM\n" - "in the last GB of RAM before the 4 GB limit (the entire space from\n" - "0xC0000000 to 0xFFFFFFFF was not usable due to being used for I/O, not\n" - "only the space from 0xF0000000 to 0xFFFFFFFF is used for I/O).\n" - "\n" - "Therefore this commit:\n" - "\n" - " * Updates the memory->reg Device Tree property with the fact that in\n" - " the first bank of RAM, memory up to 0xf0000000 can be used.\n" - "\n" - " * Updates the soc->ranges Device Tree property with the fact that the\n" - " internal registers are now mapped at 0xf1000000.\n" - "\n" - "Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>\n" - "Signed-off-by: Jason Cooper <jason@lakedaemon.net>\n" - "---\n" - " arch/arm/boot/dts/armada-xp-gp.dts | 22 ++++++++++++++++------\n" - " 1 file changed, 16 insertions(+), 6 deletions(-)\n" - "\n" - "diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts\n" - "index 274e2ad..61bda68 100644\n" - "--- a/arch/arm/boot/dts/armada-xp-gp.dts\n" - "+++ b/arch/arm/boot/dts/armada-xp-gp.dts\n" - "@@ -2,7 +2,7 @@\n" - " * Device Tree file for Marvell Armada XP development board\n" - " * (DB-MV784MP-GP)\n" - " *\n" - "- * Copyright (C) 2013 Marvell\n" - "+ * Copyright (C) 2013-2014 Marvell\n" - " *\n" - " * Lior Amsalem <alior@marvell.com>\n" - " * Gregory CLEMENT <gregory.clement@free-electrons.com>\n" - "@@ -11,6 +11,15 @@\n" - " * This file is licensed under the terms of the GNU General Public\n" - " * License version 2. This program is licensed \"as is\" without any\n" - " * warranty of any kind, whether express or implied.\n" - "+ *\n" - "+ * Note: this Device Tree assumes that the bootloader has remapped the\n" - "+ * internal registers to 0xf1000000 (instead of the default\n" - "+ * 0xd0000000). The 0xf1000000 is the default used by the recent,\n" - "+ * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier\n" - "+ * boards were delivered with an older version of the bootloader that\n" - "+ * left internal registers mapped at 0xd0000000. If you are in this\n" - "+ * situation, you should either update your bootloader (preferred\n" - "+ * solution) or the below Device Tree should be adjusted.\n" - " */\n" - " \n" - " /dts-v1/;\n" - "@@ -30,16 +39,17 @@\n" - " * 8 GB of plug-in RAM modules by default.The amount\n" - " * of memory available can be changed by the\n" - " * bootloader according the size of the module\n" - "- * actually plugged. Only 7GB are usable because\n" - "- * addresses from 0xC0000000 to 0xffffffff are used by\n" - "- * the internal registers of the SoC.\n" - "+ * actually plugged. However, memory between\n" - "+ * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is\n" - "+ * the address range used for I/O (internal registers,\n" - "+ * MBus windows).\n" - " \t\t */\n" - "-\t\treg = <0x00000000 0x00000000 0x00000000 0xC0000000>,\n" - "+\t\treg = <0x00000000 0x00000000 0x00000000 0xf0000000>,\n" - " \t\t <0x00000001 0x00000000 0x00000001 0x00000000>;\n" - " \t};\n" - " \n" - " \tsoc {\n" - "-\t\tranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000\n" - "+\t\tranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000\n" - " \t\t\t MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000\n" - " \t\t\t MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;\n" - " \n" - "-- \n" - 1.8.3.2 - "\01:7\0" - "fn\00006-irqchip-armada-370-xp-fix-invalid-cast-of-signed-val.patch\0" - "b\0" - ">From 5881c7df1167750b103a3612876c0d1c37b55345 Mon Sep 17 00:00:00 2001\n" - "From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>\n" - "Date: Tue, 8 Apr 2014 17:33:31 +0200\n" - "Subject: [PATCH 06/13] irqchip: armada-370-xp: fix invalid cast of signed\n" - " value into unsigned variable\n" - "\n" - "The armada_370_xp_alloc_msi() function returns a signed int, which is\n" - "negative on error. However, we store the return value into an\n" - "irq_hw_number_t, which is unsigned. Therefore, we actually never test\n" - "if armada_370_xp_alloc_msi() returns an error or not, which may lead\n" - "us to use hwirq numbers of as 0xffffffe4 (when\n" - "armada_370_xp_alloc_msi() returns -ENOSPC).\n" - "\n" - "This commit fixes that by storing the return value of\n" - "armada_370_xp_alloc_msi() in a signed variable.\n" - "\n" - "Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>\n" - "---\n" - " drivers/irqchip/irq-armada-370-xp.c | 3 +--\n" - " 1 file changed, 1 insertion(+), 2 deletions(-)\n" - "\n" - "diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c\n" - "index 5409564..7858729 100644\n" - "--- a/drivers/irqchip/irq-armada-370-xp.c\n" - "+++ b/drivers/irqchip/irq-armada-370-xp.c\n" - "@@ -130,8 +130,7 @@ static int armada_370_xp_setup_msi_irq(struct msi_chip *chip,\n" - " \t\t\t\t struct msi_desc *desc)\n" - " {\n" - " \tstruct msi_msg msg;\n" - "-\tirq_hw_number_t hwirq;\n" - "-\tint virq;\n" - "+\tint virq, hwirq;\n" - " \n" - " \thwirq = armada_370_xp_alloc_msi();\n" - " \tif (hwirq < 0)\n" - "-- \n" - 1.8.3.2 - "\01:8\0" - "fn\00007-irqchip-armada-370-xp-implement-the-check_device-msi.patch\0" - "b\0" - ">From 8ee3f1764fdc1c49b4199b36d21e5f40f53eca4f Mon Sep 17 00:00:00 2001\n" - "From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>\n" - "Date: Tue, 8 Apr 2014 17:35:23 +0200\n" - "Subject: [PATCH 07/13] irqchip: armada-370-xp: implement the ->check_device()\n" - " msi_chip operation\n" - "\n" - "Until now, we were leaving the ->check_device() msi_chip operation\n" - "empty, which leads the PCI core to believe that we support both MSI\n" - "and MSI-X. In fact, we do not support MSI-X, so we have to tell this\n" - "to the PCI core by providing an implementation of this operation.\n" - "\n" - "Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>\n" - "---\n" - " drivers/irqchip/irq-armada-370-xp.c | 10 ++++++++++\n" - " 1 file changed, 10 insertions(+)\n" - "\n" - "diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c\n" - "index 7858729..5d925af 100644\n" - "--- a/drivers/irqchip/irq-armada-370-xp.c\n" - "+++ b/drivers/irqchip/irq-armada-370-xp.c\n" - "@@ -160,6 +160,15 @@ static void armada_370_xp_teardown_msi_irq(struct msi_chip *chip,\n" - " \tarmada_370_xp_free_msi(d->hwirq);\n" - " }\n" - " \n" - "+static int armada_370_xp_check_msi_device(struct msi_chip *chip, struct pci_dev *dev,\n" - "+\t\t\t\t\t int nvec, int type)\n" - "+{\n" - "+\t/* We support MSI, but not MSI-X */\n" - "+\tif (type == PCI_CAP_ID_MSI)\n" - "+\t\treturn 0;\n" - "+\treturn -EINVAL;\n" - "+}\n" - "+\n" - " static struct irq_chip armada_370_xp_msi_irq_chip = {\n" - " \t.name = \"armada_370_xp_msi_irq\",\n" - " \t.irq_enable = unmask_msi_irq,\n" - "@@ -198,6 +207,7 @@ static int armada_370_xp_msi_init(struct device_node *node,\n" - " \n" - " \tmsi_chip->setup_irq = armada_370_xp_setup_msi_irq;\n" - " \tmsi_chip->teardown_irq = armada_370_xp_teardown_msi_irq;\n" - "+\tmsi_chip->check_device = armada_370_xp_check_msi_device;\n" - " \tmsi_chip->of_node = node;\n" - " \n" - " \tarmada_370_xp_msi_domain =\n" - "-- \n" - 1.8.3.2 - "\01:9\0" - "fn\00008-irqchip-armada-370-xp-Fix-releasing-of-MSIs.patch\0" - "b\0" - ">From 3521e42c3b6880fc466ef431e766d71bf77b206e Mon Sep 17 00:00:00 2001\n" - "From: Neil Greatorex <neil@fatboyfat.co.uk>\n" - "Date: Sun, 6 Apr 2014 16:10:43 +0100\n" - "Subject: [PATCH 08/13] irqchip: armada-370-xp: Fix releasing of MSIs\n" - "\n" - "Store the value of d->hwirq in a local variable as the real value is wiped out\n" - "by calling irq_dispose_mapping. Without this patch, the armada_370_xp_free_msi\n" - "function would always free MSI#0, no matter what was passed to it.\n" - "\n" - "Signed-off-by: Neil Greatorex <neil@fatboyfat.co.uk>\n" - "Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>\n" - "---\n" - " drivers/irqchip/irq-armada-370-xp.c | 4 +++-\n" - " 1 file changed, 3 insertions(+), 1 deletion(-)\n" - "\n" - "diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c\n" - "index 5d925af..939eb0d 100644\n" - "--- a/drivers/irqchip/irq-armada-370-xp.c\n" - "+++ b/drivers/irqchip/irq-armada-370-xp.c\n" - "@@ -156,8 +156,10 @@ static void armada_370_xp_teardown_msi_irq(struct msi_chip *chip,\n" - " \t\t\t\t\t unsigned int irq)\n" - " {\n" - " \tstruct irq_data *d = irq_get_irq_data(irq);\n" - "+\tunsigned long hwirq = d->hwirq;\n" - "+\n" - " \tirq_dispose_mapping(irq);\n" - "-\tarmada_370_xp_free_msi(d->hwirq);\n" - "+\tarmada_370_xp_free_msi(hwirq);\n" - " }\n" - " \n" - " static int armada_370_xp_check_msi_device(struct msi_chip *chip, struct pci_dev *dev,\n" - "-- \n" - 1.8.3.2 - "\01:10\0" - "fn\00009-pci-mvebu-fix-off-by-one-in-the-computed-size-of-the.patch\0" - "b\0" - ">From 7c1f808988da77a1d315459f735609426abb2c41 Mon Sep 17 00:00:00 2001\n" - "From: Willy Tarreau <w@1wt.eu>\n" - "Date: Wed, 9 Apr 2014 08:05:09 +0200\n" - "Subject: [PATCH 09/13] pci: mvebu: fix off-by-one in the computed size of the\n" - " mbus windows\n" - "\n" - "mvebu_pcie_handle_membase_change() and\n" - "mvebu_pcie_handle_iobase_change() do not correctly compute the window\n" - "size. PCI uses an inclusive start/end address pair, which requires a\n" - "+1 when converting to size.\n" - "\n" - "This only worked because a bug in the mbus driver allowed it to\n" - "silently accept and round up bogus sizes.\n" - "\n" - "Fix this by adding one to the computed size.\n" - "\n" - "Signed-off-by: Willy Tarreau <w@1wt.eu>\n" - "Reviewed-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>\n" - "Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>\n" - "---\n" - " drivers/pci/host/pci-mvebu.c | 4 ++--\n" - " 1 file changed, 2 insertions(+), 2 deletions(-)\n" - "\n" - "diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c\n" - "index 0e79665..eff0ab5 100644\n" - "--- a/drivers/pci/host/pci-mvebu.c\n" - "+++ b/drivers/pci/host/pci-mvebu.c\n" - "@@ -329,7 +329,7 @@ static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)\n" - " \tport->iowin_base = port->pcie->io.start + iobase;\n" - " \tport->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |\n" - " \t\t\t (port->bridge.iolimitupper << 16)) -\n" - "-\t\t\t iobase);\n" - "+\t\t\t iobase) + 1;\n" - " \n" - " \tmvebu_mbus_add_window_remap_by_id(port->io_target, port->io_attr,\n" - " \t\t\t\t\t port->iowin_base, port->iowin_size,\n" - "@@ -362,7 +362,7 @@ static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)\n" - " \tport->memwin_base = ((port->bridge.membase & 0xFFF0) << 16);\n" - " \tport->memwin_size =\n" - " \t\t(((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -\n" - "-\t\tport->memwin_base;\n" - "+\t\tport->memwin_base + 1;\n" - " \n" - " \tmvebu_mbus_add_window_by_id(port->mem_target, port->mem_attr,\n" - " \t\t\t\t port->memwin_base, port->memwin_size);\n" - "-- \n" - 1.8.3.2 - "\01:11\0" - "fn\00010-bus-mvebu-mbus-Avoid-setting-an-undefined-window-siz.patch\0" - "b\0" - ">From e3eaec9f807213a6321c44780a09187c93f0145a Mon Sep 17 00:00:00 2001\n" - "From: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>\n" - "Date: Tue, 8 Apr 2014 17:44:14 -0600\n" - "Subject: [PATCH 10/13] bus: mvebu-mbus: Avoid setting an undefined window size\n" - "\n" - "The mbus hardware requires a power of two size, and size aligned base.\n" - "Currently, if a non-power of two is passed in to the low level routines\n" - "they configure the register in a way that results in undefined behaviour.\n" - "\n" - "Call WARN and return EINVAL instead.\n" - "\n" - "Also, update the debugfs routines to show a message if there is an\n" - "invalid register setting.\n" - "\n" - "All together this makes the recent problems with silent failure\n" - "of PCI very obvious, noisy and debuggable.\n" - "\n" - "Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>\n" - "Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>\n" - "---\n" - " drivers/bus/mvebu-mbus.c | 16 ++++++++++++++++\n" - " 1 file changed, 16 insertions(+)\n" - "\n" - "diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c\n" - "index 725c461..15a398d 100644\n" - "--- a/drivers/bus/mvebu-mbus.c\n" - "+++ b/drivers/bus/mvebu-mbus.c\n" - "@@ -56,6 +56,7 @@\n" - " #include <linux/of.h>\n" - " #include <linux/of_address.h>\n" - " #include <linux/debugfs.h>\n" - "+#include <linux/log2.h>\n" - " \n" - " /*\n" - " * DDR target is the same on all platforms.\n" - "@@ -266,6 +267,17 @@ static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,\n" - " \t\tmbus->soc->win_cfg_offset(win);\n" - " \tu32 ctrl, remap_addr;\n" - " \n" - "+\tif (!is_power_of_2(size)) {\n" - "+\t\tWARN(true, \"Invalid MBus window size: 0x%zx\\n\", size);\n" - "+\t\treturn -EINVAL;\n" - "+\t}\n" - "+\n" - "+\tif ((base & (phys_addr_t)(size - 1)) != 0) {\n" - "+\t\tWARN(true, \"Invalid MBus base/size: %pa len 0x%zx\\n\", &base,\n" - "+\t\t size);\n" - "+\t\treturn -EINVAL;\n" - "+\t}\n" - "+\n" - " \tctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |\n" - " \t\t(attr << WIN_CTRL_ATTR_SHIFT) |\n" - " \t\t(target << WIN_CTRL_TGT_SHIFT) |\n" - "@@ -413,6 +425,10 @@ static int mvebu_devs_debug_show(struct seq_file *seq, void *v)\n" - " \t\t\t win, (unsigned long long)wbase,\n" - " \t\t\t (unsigned long long)(wbase + wsize), wtarget, wattr);\n" - " \n" - "+\t\tif (!is_power_of_2(wsize) ||\n" - "+\t\t ((wbase & (u64)(wsize - 1)) != 0))\n" - "+\t\t\tseq_puts(seq, \" (Invalid base/size!!)\");\n" - "+\n" - " \t\tif (win < mbus->soc->num_remappable_wins) {\n" - " \t\t\tseq_printf(seq, \" (remap %016llx)\\n\",\n" - " \t\t\t\t (unsigned long long)wremap);\n" - "-- \n" - 1.8.3.2 - "\01:12\0" - "fn\00011-bus-mvebu-mbus-allow-several-windows-with-the-same-t.patch\0" - "b\0" - ">From d6184385d76474408ad9922be57d0d47525094e0 Mon Sep 17 00:00:00 2001\n" - "From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>\n" - "Date: Thu, 10 Apr 2014 16:15:15 +0200\n" - "Subject: [PATCH 11/13] bus: mvebu-mbus: allow several windows with the same\n" - " target/attribute\n" - "\n" - "Having multiple windows with the same target and attribute is actually\n" - "legal, and can be useful for PCIe windows, when PCIe BARs have a size\n" - "that isn't a power of two, and we therefore need to create several\n" - "MBus windows to cover the PCIe BAR for a given PCIe interface.\n" - "\n" - "Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>\n" - "---\n" - " drivers/bus/mvebu-mbus.c | 6 ------\n" - " 1 file changed, 6 deletions(-)\n" - "\n" - "diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c\n" - "index 15a398d..54d339e 100644\n" - "--- a/drivers/bus/mvebu-mbus.c\n" - "+++ b/drivers/bus/mvebu-mbus.c\n" - "@@ -223,12 +223,6 @@ static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus,\n" - " \t\t */\n" - " \t\tif ((u64)base < wend && end > wbase)\n" - " \t\t\treturn 0;\n" - "-\n" - "-\t\t/*\n" - "-\t\t * Check if target/attribute conflicts\n" - "-\t\t */\n" - "-\t\tif (target == wtarget && attr == wattr)\n" - "-\t\t\treturn 0;\n" - " \t}\n" - " \n" - " \treturn 1;\n" - "-- \n" - 1.8.3.2 - "\01:13\0" - "fn\00012-pci-pci-mvebu-split-PCIe-BARs-into-multiple-MBus-win.patch\0" - "b\0" - ">From d5c41e956a19f4f7c69bc002291a866f4ad3e145 Mon Sep 17 00:00:00 2001\n" - "From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>\n" - "Date: Thu, 10 Apr 2014 16:16:16 +0200\n" - "Subject: [PATCH 12/13] pci: pci-mvebu: split PCIe BARs into multiple MBus\n" - " windows when needed\n" - "\n" - "MBus windows are used on Marvell platforms to map certain peripherals\n" - "in the physical address space. In the PCIe context, MBus windows are\n" - "needed to map PCIe I/O and memory regions in the physical address.\n" - "\n" - "However, those MBus windows can only have power of two sizes, while\n" - "PCIe BAR do not necessarily guarantee this. For this reason, the\n" - "current pci-mvebu breaks on platforms where PCIe devices have BARs\n" - "that don't sum up to a power of two size at the emulated bridge level.\n" - "\n" - "This commit fixes this by allowing the pci-mvebu driver to create\n" - "multiple contiguous MBus windows (each having a power of two size) to\n" - "cover a given PCIe BAR.\n" - "\n" - "To achieve this, two functions are added: mvebu_pcie_add_windows() and\n" - "mvebu_pcie_del_windows() to respectively add and remove all the MBus\n" - "windows that are needed to map the provided PCIe region base and\n" - "size. The emulated PCI bridge code now calls those functions, instead\n" - "of directly calling the mvebu-mbus driver functions.\n" - "\n" - "Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>\n" - "---\n" - " drivers/pci/host/pci-mvebu.c | 88 +++++++++++++++++++++++++++++++++++++-------\n" - " 1 file changed, 74 insertions(+), 14 deletions(-)\n" - "\n" - "diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c\n" - "index eff0ab5..487c926 100644\n" - "--- a/drivers/pci/host/pci-mvebu.c\n" - "+++ b/drivers/pci/host/pci-mvebu.c\n" - "@@ -291,6 +291,58 @@ static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,\n" - " \treturn PCIBIOS_SUCCESSFUL;\n" - " }\n" - " \n" - "+/*\n" - "+ * Remove windows, starting from the largest ones to the smallest\n" - "+ * ones.\n" - "+ */\n" - "+static void mvebu_pcie_del_windows(struct mvebu_pcie_port *port,\n" - "+\t\t\t\t phys_addr_t base, size_t size)\n" - "+{\n" - "+\twhile (size) {\n" - "+\t\tsize_t sz = 1 << (fls(size) - 1);\n" - "+\n" - "+\t\tmvebu_mbus_del_window(base, sz);\n" - "+\t\tbase += sz;\n" - "+\t\tsize -= sz;\n" - "+\t}\n" - "+}\n" - "+\n" - "+/*\n" - "+ * MBus windows can only have a power of two size, but PCI BARs do not\n" - "+ * have this constraint. Therefore, we have to split the PCI BAR into\n" - "+ * areas each having a power of two size. We start from the largest\n" - "+ * one (i.e highest order bit set in the size).\n" - "+ */\n" - "+static void mvebu_pcie_add_windows(struct mvebu_pcie_port *port,\n" - "+\t\t\t\t unsigned int target, unsigned int attribute,\n" - "+\t\t\t\t phys_addr_t base, size_t size,\n" - "+\t\t\t\t phys_addr_t remap)\n" - "+{\n" - "+\tsize_t size_mapped = 0;\n" - "+\n" - "+\twhile (size) {\n" - "+\t\tsize_t sz = 1 << (fls(size) - 1);\n" - "+\t\tint ret;\n" - "+\n" - "+\t\tret = mvebu_mbus_add_window_remap_by_id(target, attribute, base,\n" - "+\t\t\t\t\t\t\tsz, remap);\n" - "+\t\tif (ret) {\n" - "+\t\t\tdev_err(&port->pcie->pdev->dev,\n" - "+\t\t\t\t\"Could not create MBus window at 0x%x, size 0x%x: %d\\n\",\n" - "+\t\t\t\tbase, sz, ret);\n" - "+\t\t\tmvebu_pcie_del_windows(port, base - size_mapped,\n" - "+\t\t\t\t\t size_mapped);\n" - "+\t\t\treturn;\n" - "+\t\t}\n" - "+\n" - "+\t\tsize -= sz;\n" - "+\t\tsize_mapped += sz;\n" - "+\t\tbase += sz;\n" - "+\t\tif (remap != MVEBU_MBUS_NO_REMAP)\n" - "+\t\t\tremap += sz;\n" - "+\t}\n" - "+}\n" - "+\n" - " static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)\n" - " {\n" - " \tphys_addr_t iobase;\n" - "@@ -302,8 +354,8 @@ static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)\n" - " \n" - " \t\t/* If a window was configured, remove it */\n" - " \t\tif (port->iowin_base) {\n" - "-\t\t\tmvebu_mbus_del_window(port->iowin_base,\n" - "-\t\t\t\t\t port->iowin_size);\n" - "+\t\t\tmvebu_pcie_del_windows(port, port->iowin_base,\n" - "+\t\t\t\t\t port->iowin_size);\n" - " \t\t\tport->iowin_base = 0;\n" - " \t\t\tport->iowin_size = 0;\n" - " \t\t}\n" - "@@ -331,9 +383,9 @@ static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)\n" - " \t\t\t (port->bridge.iolimitupper << 16)) -\n" - " \t\t\t iobase) + 1;\n" - " \n" - "-\tmvebu_mbus_add_window_remap_by_id(port->io_target, port->io_attr,\n" - "-\t\t\t\t\t port->iowin_base, port->iowin_size,\n" - "-\t\t\t\t\t iobase);\n" - "+\tmvebu_pcie_add_windows(port, port->io_target, port->io_attr,\n" - "+\t\t\t port->iowin_base, port->iowin_size,\n" - "+\t\t\t iobase);\n" - " }\n" - " \n" - " static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)\n" - "@@ -344,8 +396,8 @@ static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)\n" - " \n" - " \t\t/* If a window was configured, remove it */\n" - " \t\tif (port->memwin_base) {\n" - "-\t\t\tmvebu_mbus_del_window(port->memwin_base,\n" - "-\t\t\t\t\t port->memwin_size);\n" - "+\t\t\tmvebu_pcie_del_windows(port, port->memwin_base,\n" - "+\t\t\t\t\t port->memwin_size);\n" - " \t\t\tport->memwin_base = 0;\n" - " \t\t\tport->memwin_size = 0;\n" - " \t\t}\n" - "@@ -364,8 +416,9 @@ static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)\n" - " \t\t(((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -\n" - " \t\tport->memwin_base + 1;\n" - " \n" - "-\tmvebu_mbus_add_window_by_id(port->mem_target, port->mem_attr,\n" - "-\t\t\t\t port->memwin_base, port->memwin_size);\n" - "+\tmvebu_pcie_add_windows(port, port->mem_target, port->mem_attr,\n" - "+\t\t\t port->memwin_base, port->memwin_size,\n" - "+\t\t\t MVEBU_MBUS_NO_REMAP);\n" - " }\n" - " \n" - " /*\n" - "@@ -721,14 +774,21 @@ static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,\n" - " \n" - " \t/*\n" - " \t * On the PCI-to-PCI bridge side, the I/O windows must have at\n" - "-\t * least a 64 KB size and be aligned on their size, and the\n" - "-\t * memory windows must have at least a 1 MB size and be\n" - "-\t * aligned on their size\n" - "+\t * least a 64 KB size and the memory windows must have at\n" - "+\t * least a 1 MB size. Moreover, MBus windows need to have a\n" - "+\t * base address aligned on their size, and their size must be\n" - "+\t * a power of two. This means that if the BAR doesn't have a\n" - "+\t * power of two size, several MBus windows will actually be\n" - "+\t * created. We need to ensure that the biggest MBus window\n" - "+\t * (which will be the first one) is aligned on its size, which\n" - "+\t * explains the rounddown_pow_of_two() being done here.\n" - " \t */\n" - " \tif (res->flags & IORESOURCE_IO)\n" - "-\t\treturn round_up(start, max_t(resource_size_t, SZ_64K, size));\n" - "+\t\treturn round_up(start, max_t(resource_size_t, SZ_64K,\n" - "+\t\t\t\t\t rounddown_pow_of_two(size)));\n" - " \telse if (res->flags & IORESOURCE_MEM)\n" - "-\t\treturn round_up(start, max_t(resource_size_t, SZ_1M, size));\n" - "+\t\treturn round_up(start, max_t(resource_size_t, SZ_1M,\n" - "+\t\t\t\t\t rounddown_pow_of_two(size)));\n" - " \telse\n" - " \t\treturn start;\n" - " }\n" - "-- \n" - 1.8.3.2 - "\01:14\0" - "fn\00013-pci-pci-mvebu-wait-for-a-device-to-appear-to-fix-clo.patch\0" - "b\0" - ">From 72706b22617da7ef8dcf1924f4c204383111401c Mon Sep 17 00:00:00 2001\n" - "From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>\n" - "Date: Fri, 11 Apr 2014 15:22:36 +0200\n" - "Subject: [PATCH 13/13] pci: pci-mvebu: wait for a device to appear to fix\n" - " clock issues\n" - "\n" - "With the introduction of the mvebu-soc-id mechanism in\n" - "arch/arm/mach-mvebu/, the PCIe clocks can be gated during early boot,\n" - "and then re-enabled later when the pci-mvebu driver gets\n" - "called. However, after the clock has been enabled, it takes some time\n" - "for the PCIe device to become visible: this is causing problems on\n" - "some platforms where PCIe devices may not be detected at boot time due\n" - "to this.\n" - "\n" - "To fix this, this commit introduces a simple loop that waits for a\n" - "valid device to actually show up on each PCIe interface for which the\n" - "link is up.\n" - "\n" - "It fixes a problem reported both by Gregory Clement and Neil\n" - "Greatorex, which were seeing all PCIe devices detected when\n" - "earlyprintk was enabled, but one of the device was missing when\n" - "earlyprintk was disabled. This was due to the fact that earlyprintk\n" - "was slowing down the boot sufficiently to make the problem invisible.\n" - "\n" - "Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>\n" - "Reported-by: Neil Greatorex <neil@fatboyfat.co.uk>\n" - "Reported-by: Gregory CLEMENT <gregory.clement@free-electrons.com>\n" - "---\n" - " drivers/pci/host/pci-mvebu.c | 39 +++++++++++++++++++++++++++++++++++++++\n" - " 1 file changed, 39 insertions(+)\n" - "\n" - "diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c\n" - "index 487c926..008d718 100644\n" - "--- a/drivers/pci/host/pci-mvebu.c\n" - "+++ b/drivers/pci/host/pci-mvebu.c\n" - "@@ -21,6 +21,7 @@\n" - " #include <linux/of_gpio.h>\n" - " #include <linux/of_pci.h>\n" - " #include <linux/of_platform.h>\n" - "+#include <linux/clk-provider.h>\n" - " \n" - " /*\n" - " * PCIe unit register offsets.\n" - "@@ -162,6 +163,14 @@ static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)\n" - " \tmvebu_writel(port, stat, PCIE_STAT_OFF);\n" - " }\n" - " \n" - "+static u32 mvebu_pcie_get_local_bus_nr(struct mvebu_pcie_port *port)\n" - "+{\n" - "+\tu32 stat;\n" - "+\n" - "+\tstat = mvebu_readl(port, PCIE_STAT_OFF);\n" - "+\treturn (stat & PCIE_STAT_BUS) >> 8;\n" - "+}\n" - "+\n" - " static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)\n" - " {\n" - " \tu32 stat;\n" - "@@ -172,6 +181,30 @@ static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)\n" - " \tmvebu_writel(port, stat, PCIE_STAT_OFF);\n" - " }\n" - " \n" - "+static void mvebu_pcie_wait_dev(struct mvebu_pcie_port *port)\n" - "+{\n" - "+\tint tries;\n" - "+\n" - "+\tfor (tries = 0; tries < 1000; tries++) {\n" - "+\t\tu32 vpid;\n" - "+\n" - "+\t\tmvebu_writel(port,\n" - "+\t\t\t PCIE_CONF_ADDR(mvebu_pcie_get_local_bus_nr(port),\n" - "+\t\t\t\t\t PCI_DEVFN(0, 0), PCI_VENDOR_ID),\n" - "+\t\t\t PCIE_CONF_ADDR_OFF);\n" - "+\t\tvpid = mvebu_readl(port, PCIE_CONF_DATA_OFF);\n" - "+\n" - "+\t\tif (vpid != 0xffffffff)\n" - "+\t\t\tbreak;\n" - "+\n" - "+\t\tudelay(100);\n" - "+\t}\n" - "+\n" - "+\tif (tries >= 1000)\n" - "+\t\tdev_warn(&port->pcie->pdev->dev,\n" - "+\t\t\t \"timeout when looking for the PCIe device\\n\");\n" - "+}\n" - "+\n" - " /*\n" - " * Setup PCIE BARs and Address Decode Wins:\n" - " * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks\n" - "@@ -951,6 +984,7 @@ static int mvebu_pcie_probe(struct platform_device *pdev)\n" - " \tfor_each_child_of_node(pdev->dev.of_node, child) {\n" - " \t\tstruct mvebu_pcie_port *port = &pcie->ports[i];\n" - " \t\tenum of_gpio_flags flags;\n" - "+\t\tint linkup;\n" - " \n" - " \t\tif (!of_device_is_available(child))\n" - " \t\t\tcontinue;\n" - "@@ -1035,8 +1069,13 @@ static int mvebu_pcie_probe(struct platform_device *pdev)\n" - " \t\t\tcontinue;\n" - " \t\t}\n" - " \n" - "+\t\tlinkup = mvebu_pcie_link_up(port);\n" - "+\n" - " \t\tmvebu_pcie_set_local_dev_nr(port, 1);\n" - " \n" - "+\t\tif (linkup)\n" - "+\t\t\tmvebu_pcie_wait_dev(port);\n" - "+\n" - " \t\tport->dn = child;\n" - " \t\tspin_lock_init(&port->conf_lock);\n" - " \t\tmvebu_sw_pci_bridge_init(port);\n" - "-- \n" - 1.8.3.2 - "\01:15\0" - "fn\0combined.patch\0" - "b\0" - "diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi\n" - "index 74b5964..2188ce6 100644\n" - "--- a/arch/arm/boot/dts/armada-370-xp.dtsi\n" - "+++ b/arch/arm/boot/dts/armada-370-xp.dtsi\n" - "@@ -44,8 +44,8 @@\n" - " \t\t#size-cells = <1>;\n" - " \t\tcontroller = <&mbusc>;\n" - " \t\tinterrupt-parent = <&mpic>;\n" - "-\t\tpcie-mem-aperture = <0xe0000000 0x8000000>;\n" - "-\t\tpcie-io-aperture = <0xe8000000 0x100000>;\n" - "+\t\tpcie-mem-aperture = <0xf8000000 0x7e00000>;\n" - "+\t\tpcie-io-aperture = <0xffe00000 0x100000>;\n" - " \n" - " \t\tdevbus-bootcs {\n" - " \t\t\tcompatible = \"marvell,mvebu-devbus\";\n" - "diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts\n" - "index bcf6d79..448373c 100644\n" - "--- a/arch/arm/boot/dts/armada-xp-db.dts\n" - "+++ b/arch/arm/boot/dts/armada-xp-db.dts\n" - "@@ -2,7 +2,7 @@\n" - " * Device Tree file for Marvell Armada XP evaluation board\n" - " * (DB-78460-BP)\n" - " *\n" - "- * Copyright (C) 2012 Marvell\n" - "+ * Copyright (C) 2012-2014 Marvell\n" - " *\n" - " * Lior Amsalem <alior@marvell.com>\n" - " * Gregory CLEMENT <gregory.clement@free-electrons.com>\n" - "@@ -11,6 +11,15 @@\n" - " * This file is licensed under the terms of the GNU General Public\n" - " * License version 2. This program is licensed \"as is\" without any\n" - " * warranty of any kind, whether express or implied.\n" - "+ *\n" - "+ * Note: this Device Tree assumes that the bootloader has remapped the\n" - "+ * internal registers to 0xf1000000 (instead of the default\n" - "+ * 0xd0000000). The 0xf1000000 is the default used by the recent,\n" - "+ * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier\n" - "+ * boards were delivered with an older version of the bootloader that\n" - "+ * left internal registers mapped at 0xd0000000. If you are in this\n" - "+ * situation, you should either update your bootloader (preferred\n" - "+ * solution) or the below Device Tree should be adjusted.\n" - " */\n" - " \n" - " /dts-v1/;\n" - "@@ -30,7 +39,7 @@\n" - " \t};\n" - " \n" - " \tsoc {\n" - "-\t\tranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000\n" - "+\t\tranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000\n" - " \t\t\t MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000\n" - " \t\t\t MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;\n" - " \n" - "diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts\n" - "index 274e2ad..61bda68 100644\n" - "--- a/arch/arm/boot/dts/armada-xp-gp.dts\n" - "+++ b/arch/arm/boot/dts/armada-xp-gp.dts\n" - "@@ -2,7 +2,7 @@\n" - " * Device Tree file for Marvell Armada XP development board\n" - " * (DB-MV784MP-GP)\n" - " *\n" - "- * Copyright (C) 2013 Marvell\n" - "+ * Copyright (C) 2013-2014 Marvell\n" - " *\n" - " * Lior Amsalem <alior@marvell.com>\n" - " * Gregory CLEMENT <gregory.clement@free-electrons.com>\n" - "@@ -11,6 +11,15 @@\n" - " * This file is licensed under the terms of the GNU General Public\n" - " * License version 2. This program is licensed \"as is\" without any\n" - " * warranty of any kind, whether express or implied.\n" - "+ *\n" - "+ * Note: this Device Tree assumes that the bootloader has remapped the\n" - "+ * internal registers to 0xf1000000 (instead of the default\n" - "+ * 0xd0000000). The 0xf1000000 is the default used by the recent,\n" - "+ * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier\n" - "+ * boards were delivered with an older version of the bootloader that\n" - "+ * left internal registers mapped at 0xd0000000. If you are in this\n" - "+ * situation, you should either update your bootloader (preferred\n" - "+ * solution) or the below Device Tree should be adjusted.\n" - " */\n" - " \n" - " /dts-v1/;\n" - "@@ -30,16 +39,17 @@\n" - " * 8 GB of plug-in RAM modules by default.The amount\n" - " * of memory available can be changed by the\n" - " * bootloader according the size of the module\n" - "- * actually plugged. Only 7GB are usable because\n" - "- * addresses from 0xC0000000 to 0xffffffff are used by\n" - "- * the internal registers of the SoC.\n" - "+ * actually plugged. However, memory between\n" - "+ * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is\n" - "+ * the address range used for I/O (internal registers,\n" - "+ * MBus windows).\n" - " \t\t */\n" - "-\t\treg = <0x00000000 0x00000000 0x00000000 0xC0000000>,\n" - "+\t\treg = <0x00000000 0x00000000 0x00000000 0xf0000000>,\n" - " \t\t <0x00000001 0x00000000 0x00000001 0x00000000>;\n" - " \t};\n" - " \n" - " \tsoc {\n" - "-\t\tranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000\n" - "+\t\tranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000\n" - " \t\t\t MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000\n" - " \t\t\t MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;\n" - " \n" - "diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c\n" - "index 725c461..54d339e 100644\n" - "--- a/drivers/bus/mvebu-mbus.c\n" - "+++ b/drivers/bus/mvebu-mbus.c\n" - "@@ -56,6 +56,7 @@\n" - " #include <linux/of.h>\n" - " #include <linux/of_address.h>\n" - " #include <linux/debugfs.h>\n" - "+#include <linux/log2.h>\n" - " \n" - " /*\n" - " * DDR target is the same on all platforms.\n" - "@@ -222,12 +223,6 @@ static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus,\n" - " \t\t */\n" - " \t\tif ((u64)base < wend && end > wbase)\n" - " \t\t\treturn 0;\n" - "-\n" - "-\t\t/*\n" - "-\t\t * Check if target/attribute conflicts\n" - "-\t\t */\n" - "-\t\tif (target == wtarget && attr == wattr)\n" - "-\t\t\treturn 0;\n" - " \t}\n" - " \n" - " \treturn 1;\n" - "@@ -266,6 +261,17 @@ static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,\n" - " \t\tmbus->soc->win_cfg_offset(win);\n" - " \tu32 ctrl, remap_addr;\n" - " \n" - "+\tif (!is_power_of_2(size)) {\n" - "+\t\tWARN(true, \"Invalid MBus window size: 0x%zx\\n\", size);\n" - "+\t\treturn -EINVAL;\n" - "+\t}\n" - "+\n" - "+\tif ((base & (phys_addr_t)(size - 1)) != 0) {\n" - "+\t\tWARN(true, \"Invalid MBus base/size: %pa len 0x%zx\\n\", &base,\n" - "+\t\t size);\n" - "+\t\treturn -EINVAL;\n" - "+\t}\n" - "+\n" - " \tctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |\n" - " \t\t(attr << WIN_CTRL_ATTR_SHIFT) |\n" - " \t\t(target << WIN_CTRL_TGT_SHIFT) |\n" - "@@ -413,6 +419,10 @@ static int mvebu_devs_debug_show(struct seq_file *seq, void *v)\n" - " \t\t\t win, (unsigned long long)wbase,\n" - " \t\t\t (unsigned long long)(wbase + wsize), wtarget, wattr);\n" - " \n" - "+\t\tif (!is_power_of_2(wsize) ||\n" - "+\t\t ((wbase & (u64)(wsize - 1)) != 0))\n" - "+\t\t\tseq_puts(seq, \" (Invalid base/size!!)\");\n" - "+\n" - " \t\tif (win < mbus->soc->num_remappable_wins) {\n" - " \t\t\tseq_printf(seq, \" (remap %016llx)\\n\",\n" - " \t\t\t\t (unsigned long long)wremap);\n" - "diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c\n" - "index 5409564..939eb0d 100644\n" - "--- a/drivers/irqchip/irq-armada-370-xp.c\n" - "+++ b/drivers/irqchip/irq-armada-370-xp.c\n" - "@@ -130,8 +130,7 @@ static int armada_370_xp_setup_msi_irq(struct msi_chip *chip,\n" - " \t\t\t\t struct msi_desc *desc)\n" - " {\n" - " \tstruct msi_msg msg;\n" - "-\tirq_hw_number_t hwirq;\n" - "-\tint virq;\n" - "+\tint virq, hwirq;\n" - " \n" - " \thwirq = armada_370_xp_alloc_msi();\n" - " \tif (hwirq < 0)\n" - "@@ -157,8 +156,19 @@ static void armada_370_xp_teardown_msi_irq(struct msi_chip *chip,\n" - " \t\t\t\t\t unsigned int irq)\n" - " {\n" - " \tstruct irq_data *d = irq_get_irq_data(irq);\n" - "+\tunsigned long hwirq = d->hwirq;\n" - "+\n" - " \tirq_dispose_mapping(irq);\n" - "-\tarmada_370_xp_free_msi(d->hwirq);\n" - "+\tarmada_370_xp_free_msi(hwirq);\n" - "+}\n" - "+\n" - "+static int armada_370_xp_check_msi_device(struct msi_chip *chip, struct pci_dev *dev,\n" - "+\t\t\t\t\t int nvec, int type)\n" - "+{\n" - "+\t/* We support MSI, but not MSI-X */\n" - "+\tif (type == PCI_CAP_ID_MSI)\n" - "+\t\treturn 0;\n" - "+\treturn -EINVAL;\n" - " }\n" - " \n" - " static struct irq_chip armada_370_xp_msi_irq_chip = {\n" - "@@ -199,6 +209,7 @@ static int armada_370_xp_msi_init(struct device_node *node,\n" - " \n" - " \tmsi_chip->setup_irq = armada_370_xp_setup_msi_irq;\n" - " \tmsi_chip->teardown_irq = armada_370_xp_teardown_msi_irq;\n" - "+\tmsi_chip->check_device = armada_370_xp_check_msi_device;\n" - " \tmsi_chip->of_node = node;\n" - " \n" - " \tarmada_370_xp_msi_domain =\n" - "diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c\n" - "index 46d31a4..d9c7eb2 100644\n" - "--- a/drivers/net/ethernet/intel/igb/igb_main.c\n" - "+++ b/drivers/net/ethernet/intel/igb/igb_main.c\n" - "@@ -1014,6 +1014,12 @@ static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)\n" - " {\n" - " \tstruct igb_q_vector *q_vector = adapter->q_vector[v_idx];\n" - " \n" - "+\t/* Coming from igb_set_interrupt_capability, the vectors are not yet\n" - "+\t * allocated. So, q_vector is NULL so we should stop here.\n" - "+\t */\n" - "+\tif (!q_vector)\n" - "+\t\treturn;\n" - "+\n" - " \tif (q_vector->tx.ring)\n" - " \t\tadapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;\n" - " \n" - "@@ -1121,6 +1127,7 @@ static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)\n" - " \n" - " \t/* If we can't do MSI-X, try MSI */\n" - " msi_only:\n" - "+\tadapter->flags &= ~IGB_FLAG_HAS_MSIX;\n" - " #ifdef CONFIG_PCI_IOV\n" - " \t/* disable SR-IOV for non MSI-X configurations */\n" - " \tif (adapter->vf_data) {\n" - "diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c\n" - "index 0e79665..008d718 100644\n" - "--- a/drivers/pci/host/pci-mvebu.c\n" - "+++ b/drivers/pci/host/pci-mvebu.c\n" - "@@ -21,6 +21,7 @@\n" - " #include <linux/of_gpio.h>\n" - " #include <linux/of_pci.h>\n" - " #include <linux/of_platform.h>\n" - "+#include <linux/clk-provider.h>\n" - " \n" - " /*\n" - " * PCIe unit register offsets.\n" - "@@ -162,6 +163,14 @@ static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)\n" - " \tmvebu_writel(port, stat, PCIE_STAT_OFF);\n" - " }\n" - " \n" - "+static u32 mvebu_pcie_get_local_bus_nr(struct mvebu_pcie_port *port)\n" - "+{\n" - "+\tu32 stat;\n" - "+\n" - "+\tstat = mvebu_readl(port, PCIE_STAT_OFF);\n" - "+\treturn (stat & PCIE_STAT_BUS) >> 8;\n" - "+}\n" - "+\n" - " static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)\n" - " {\n" - " \tu32 stat;\n" - "@@ -172,6 +181,30 @@ static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)\n" - " \tmvebu_writel(port, stat, PCIE_STAT_OFF);\n" - " }\n" - " \n" - "+static void mvebu_pcie_wait_dev(struct mvebu_pcie_port *port)\n" - "+{\n" - "+\tint tries;\n" - "+\n" - "+\tfor (tries = 0; tries < 1000; tries++) {\n" - "+\t\tu32 vpid;\n" - "+\n" - "+\t\tmvebu_writel(port,\n" - "+\t\t\t PCIE_CONF_ADDR(mvebu_pcie_get_local_bus_nr(port),\n" - "+\t\t\t\t\t PCI_DEVFN(0, 0), PCI_VENDOR_ID),\n" - "+\t\t\t PCIE_CONF_ADDR_OFF);\n" - "+\t\tvpid = mvebu_readl(port, PCIE_CONF_DATA_OFF);\n" - "+\n" - "+\t\tif (vpid != 0xffffffff)\n" - "+\t\t\tbreak;\n" - "+\n" - "+\t\tudelay(100);\n" - "+\t}\n" - "+\n" - "+\tif (tries >= 1000)\n" - "+\t\tdev_warn(&port->pcie->pdev->dev,\n" - "+\t\t\t \"timeout when looking for the PCIe device\\n\");\n" - "+}\n" - "+\n" - " /*\n" - " * Setup PCIE BARs and Address Decode Wins:\n" - " * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks\n" - "@@ -291,6 +324,58 @@ static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,\n" - " \treturn PCIBIOS_SUCCESSFUL;\n" - " }\n" - " \n" - "+/*\n" - "+ * Remove windows, starting from the largest ones to the smallest\n" - "+ * ones.\n" - "+ */\n" - "+static void mvebu_pcie_del_windows(struct mvebu_pcie_port *port,\n" - "+\t\t\t\t phys_addr_t base, size_t size)\n" - "+{\n" - "+\twhile (size) {\n" - "+\t\tsize_t sz = 1 << (fls(size) - 1);\n" - "+\n" - "+\t\tmvebu_mbus_del_window(base, sz);\n" - "+\t\tbase += sz;\n" - "+\t\tsize -= sz;\n" - "+\t}\n" - "+}\n" - "+\n" - "+/*\n" - "+ * MBus windows can only have a power of two size, but PCI BARs do not\n" - "+ * have this constraint. Therefore, we have to split the PCI BAR into\n" - "+ * areas each having a power of two size. We start from the largest\n" - "+ * one (i.e highest order bit set in the size).\n" - "+ */\n" - "+static void mvebu_pcie_add_windows(struct mvebu_pcie_port *port,\n" - "+\t\t\t\t unsigned int target, unsigned int attribute,\n" - "+\t\t\t\t phys_addr_t base, size_t size,\n" - "+\t\t\t\t phys_addr_t remap)\n" - "+{\n" - "+\tsize_t size_mapped = 0;\n" - "+\n" - "+\twhile (size) {\n" - "+\t\tsize_t sz = 1 << (fls(size) - 1);\n" - "+\t\tint ret;\n" - "+\n" - "+\t\tret = mvebu_mbus_add_window_remap_by_id(target, attribute, base,\n" - "+\t\t\t\t\t\t\tsz, remap);\n" - "+\t\tif (ret) {\n" - "+\t\t\tdev_err(&port->pcie->pdev->dev,\n" - "+\t\t\t\t\"Could not create MBus window at 0x%x, size 0x%x: %d\\n\",\n" - "+\t\t\t\tbase, sz, ret);\n" - "+\t\t\tmvebu_pcie_del_windows(port, base - size_mapped,\n" - "+\t\t\t\t\t size_mapped);\n" - "+\t\t\treturn;\n" - "+\t\t}\n" - "+\n" - "+\t\tsize -= sz;\n" - "+\t\tsize_mapped += sz;\n" - "+\t\tbase += sz;\n" - "+\t\tif (remap != MVEBU_MBUS_NO_REMAP)\n" - "+\t\t\tremap += sz;\n" - "+\t}\n" - "+}\n" - "+\n" - " static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)\n" - " {\n" - " \tphys_addr_t iobase;\n" - "@@ -302,8 +387,8 @@ static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)\n" - " \n" - " \t\t/* If a window was configured, remove it */\n" - " \t\tif (port->iowin_base) {\n" - "-\t\t\tmvebu_mbus_del_window(port->iowin_base,\n" - "-\t\t\t\t\t port->iowin_size);\n" - "+\t\t\tmvebu_pcie_del_windows(port, port->iowin_base,\n" - "+\t\t\t\t\t port->iowin_size);\n" - " \t\t\tport->iowin_base = 0;\n" - " \t\t\tport->iowin_size = 0;\n" - " \t\t}\n" - "@@ -329,11 +414,11 @@ static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)\n" - " \tport->iowin_base = port->pcie->io.start + iobase;\n" - " \tport->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |\n" - " \t\t\t (port->bridge.iolimitupper << 16)) -\n" - "-\t\t\t iobase);\n" - "+\t\t\t iobase) + 1;\n" - " \n" - "-\tmvebu_mbus_add_window_remap_by_id(port->io_target, port->io_attr,\n" - "-\t\t\t\t\t port->iowin_base, port->iowin_size,\n" - "-\t\t\t\t\t iobase);\n" - "+\tmvebu_pcie_add_windows(port, port->io_target, port->io_attr,\n" - "+\t\t\t port->iowin_base, port->iowin_size,\n" - "+\t\t\t iobase);\n" - " }\n" - " \n" - " static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)\n" - "@@ -344,8 +429,8 @@ static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)\n" - " \n" - " \t\t/* If a window was configured, remove it */\n" - " \t\tif (port->memwin_base) {\n" - "-\t\t\tmvebu_mbus_del_window(port->memwin_base,\n" - "-\t\t\t\t\t port->memwin_size);\n" - "+\t\t\tmvebu_pcie_del_windows(port, port->memwin_base,\n" - "+\t\t\t\t\t port->memwin_size);\n" - " \t\t\tport->memwin_base = 0;\n" - " \t\t\tport->memwin_size = 0;\n" - " \t\t}\n" - "@@ -362,10 +447,11 @@ static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)\n" - " \tport->memwin_base = ((port->bridge.membase & 0xFFF0) << 16);\n" - " \tport->memwin_size =\n" - " \t\t(((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -\n" - "-\t\tport->memwin_base;\n" - "+\t\tport->memwin_base + 1;\n" - " \n" - "-\tmvebu_mbus_add_window_by_id(port->mem_target, port->mem_attr,\n" - "-\t\t\t\t port->memwin_base, port->memwin_size);\n" - "+\tmvebu_pcie_add_windows(port, port->mem_target, port->mem_attr,\n" - "+\t\t\t port->memwin_base, port->memwin_size,\n" - "+\t\t\t MVEBU_MBUS_NO_REMAP);\n" - " }\n" - " \n" - " /*\n" - "@@ -721,14 +807,21 @@ static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,\n" - " \n" - " \t/*\n" - " \t * On the PCI-to-PCI bridge side, the I/O windows must have at\n" - "-\t * least a 64 KB size and be aligned on their size, and the\n" - "-\t * memory windows must have at least a 1 MB size and be\n" - "-\t * aligned on their size\n" - "+\t * least a 64 KB size and the memory windows must have at\n" - "+\t * least a 1 MB size. Moreover, MBus windows need to have a\n" - "+\t * base address aligned on their size, and their size must be\n" - "+\t * a power of two. This means that if the BAR doesn't have a\n" - "+\t * power of two size, several MBus windows will actually be\n" - "+\t * created. We need to ensure that the biggest MBus window\n" - "+\t * (which will be the first one) is aligned on its size, which\n" - "+\t * explains the rounddown_pow_of_two() being done here.\n" - " \t */\n" - " \tif (res->flags & IORESOURCE_IO)\n" - "-\t\treturn round_up(start, max_t(resource_size_t, SZ_64K, size));\n" - "+\t\treturn round_up(start, max_t(resource_size_t, SZ_64K,\n" - "+\t\t\t\t\t rounddown_pow_of_two(size)));\n" - " \telse if (res->flags & IORESOURCE_MEM)\n" - "-\t\treturn round_up(start, max_t(resource_size_t, SZ_1M, size));\n" - "+\t\treturn round_up(start, max_t(resource_size_t, SZ_1M,\n" - "+\t\t\t\t\t rounddown_pow_of_two(size)));\n" - " \telse\n" - " \t\treturn start;\n" - " }\n" - "@@ -891,6 +984,7 @@ static int mvebu_pcie_probe(struct platform_device *pdev)\n" - " \tfor_each_child_of_node(pdev->dev.of_node, child) {\n" - " \t\tstruct mvebu_pcie_port *port = &pcie->ports[i];\n" - " \t\tenum of_gpio_flags flags;\n" - "+\t\tint linkup;\n" - " \n" - " \t\tif (!of_device_is_available(child))\n" - " \t\t\tcontinue;\n" - "@@ -975,8 +1069,13 @@ static int mvebu_pcie_probe(struct platform_device *pdev)\n" - " \t\t\tcontinue;\n" - " \t\t}\n" - " \n" - "+\t\tlinkup = mvebu_pcie_link_up(port);\n" - "+\n" - " \t\tmvebu_pcie_set_local_dev_nr(port, 1);\n" - " \n" - "+\t\tif (linkup)\n" - "+\t\t\tmvebu_pcie_wait_dev(port);\n" - "+\n" - " \t\tport->dn = child;\n" - " \t\tspin_lock_init(&port->conf_lock);\n" - " \t\tmvebu_sw_pci_bridge_init(port);" + "http://free-electrons.com\n" + "-------------- next part --------------\n" + "A non-text attachment was scrubbed...\n" + "Name: 0001-igb-Fix-Null-pointer-dereference-in-igb_reset_q_vect.patch\n" + "Type: text/x-patch\n" + "Size: 1808 bytes\n" + "Desc: not available\n" + "URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140411/1b58ef39/attachment-0014.bin>\n" + "-------------- next part --------------\n" + "A non-text attachment was scrubbed...\n" + "Name: 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