From: Daniel Vetter <daniel@ffwll.ch>
To: Zhao Yakui <yakui.zhao@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH V2 1/6] drm/i915: Split the BDW device definition to prepare for dual BSD rings on BDW GT3
Date: Mon, 14 Apr 2014 09:09:34 +0200 [thread overview]
Message-ID: <20140414070934.GD8068@phenom.ffwll.local> (raw)
In-Reply-To: <1397449304-3224-2-git-send-email-yakui.zhao@intel.com>
On Mon, Apr 14, 2014 at 12:21:39PM +0800, Zhao Yakui wrote:
> V1->V2: Follow Daniel's comment to consider the stolen check for BDW in
> kernel/early-quirks.c
Small style nit: We usually put the patch changelog at the end of the
commit message. That way the core commit message is clearly separated from
the per-patch changelog. In rare cases there's some confusion otherwise.
No need to resend just for that.
-Daniel
>
> Based on the hardware spec, the BDW GT3 has the different configuration
> with the BDW GT1/GT2. So split the BDW device info definition.
> This is to do the preparation for adding the Dual BSD rings on BDW GT3 machine.
>
> Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 26 ++++++++++++++++++++++++--
> include/drm/i915_pciids.h | 22 +++++++++++++++++-----
> 2 files changed, 41 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 5d8250f..17fbbe5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -279,6 +279,26 @@ static const struct intel_device_info intel_broadwell_m_info = {
> GEN_DEFAULT_PIPEOFFSETS,
> };
>
> +static const struct intel_device_info intel_broadwell_gt3d_info = {
> + .gen = 8, .num_pipes = 3,
> + .need_gfx_hws = 1, .has_hotplug = 1,
> + .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
> + .has_llc = 1,
> + .has_ddi = 1,
> + .has_fbc = 1,
> + GEN_DEFAULT_PIPEOFFSETS,
> +};
> +
> +static const struct intel_device_info intel_broadwell_gt3m_info = {
> + .gen = 8, .is_mobile = 1, .num_pipes = 3,
> + .need_gfx_hws = 1, .has_hotplug = 1,
> + .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
> + .has_llc = 1,
> + .has_ddi = 1,
> + .has_fbc = 1,
> + GEN_DEFAULT_PIPEOFFSETS,
> +};
> +
> /*
> * Make sure any device matches here are from most specific to most
> * general. For example, since the Quanta match is based on the subsystem
> @@ -311,8 +331,10 @@ static const struct intel_device_info intel_broadwell_m_info = {
> INTEL_HSW_M_IDS(&intel_haswell_m_info), \
> INTEL_VLV_M_IDS(&intel_valleyview_m_info), \
> INTEL_VLV_D_IDS(&intel_valleyview_d_info), \
> - INTEL_BDW_M_IDS(&intel_broadwell_m_info), \
> - INTEL_BDW_D_IDS(&intel_broadwell_d_info)
> + INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \
> + INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \
> + INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
> + INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info)
>
> static const struct pci_device_id pciidlist[] = { /* aka */
> INTEL_PCI_IDS,
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 940ece4..24f3cad 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -223,14 +223,26 @@
> _INTEL_BDW_D(gt, 0x160A, info), /* Server */ \
> _INTEL_BDW_D(gt, 0x160D, info) /* Workstation */
>
> -#define INTEL_BDW_M_IDS(info) \
> +#define INTEL_BDW_GT12M_IDS(info) \
> _INTEL_BDW_M_IDS(1, info), \
> - _INTEL_BDW_M_IDS(2, info), \
> - _INTEL_BDW_M_IDS(3, info)
> + _INTEL_BDW_M_IDS(2, info)
>
> -#define INTEL_BDW_D_IDS(info) \
> +#define INTEL_BDW_GT12D_IDS(info) \
> _INTEL_BDW_D_IDS(1, info), \
> - _INTEL_BDW_D_IDS(2, info), \
> + _INTEL_BDW_D_IDS(2, info)
> +
> +#define INTEL_BDW_GT3M_IDS(info) \
> + _INTEL_BDW_M_IDS(3, info)
> +
> +#define INTEL_BDW_GT3D_IDS(info) \
> _INTEL_BDW_D_IDS(3, info)
>
> +#define INTEL_BDW_M_IDS(info) \
> + INTEL_BDW_GT12M_IDS(info), \
> + INTEL_BDW_GT3M_IDS(info)
> +
> +#define INTEL_BDW_D_IDS(info) \
> + INTEL_BDW_GT12D_IDS(info), \
> + INTEL_BDW_GT3D_IDS(info)
> +
> #endif /* _I915_PCIIDS_H */
> --
> 1.7.10.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
next prev parent reply other threads:[~2014-04-14 7:09 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-04-14 4:21 [PATCH V2 0/6] drm/i915: Add the support of dual BSD rings on BDW GT3 Zhao Yakui
2014-04-14 4:21 ` [PATCH V2 1/6] drm/i915: Split the BDW device definition to prepare for " Zhao Yakui
2014-04-14 7:09 ` Daniel Vetter [this message]
2014-04-14 7:14 ` Zhao Yakui
2014-04-14 4:21 ` [PATCH V2 2/6] drm/i915:Initialize the second BSD ring on BDW GT3 machine Zhao Yakui
2014-04-14 4:21 ` [PATCH V2 3/6] drm/i915:Handle the irq interrupt for the second BSD ring Zhao Yakui
2014-04-14 4:21 ` [PATCH V2 4/6] drm/i915: Add the VCS2 switch in Intel_ring_setup_status_page for Gen7 to remove the switch check warning Zhao Yakui
2014-04-14 4:21 ` [PATCH V2 5/6] drm/i915: Update the restrict check to filter out wrong Ring ID passed by user-space Zhao Yakui
2014-04-14 4:21 ` [PATCH V2 6/6] drm/i915:Use the coarse ping-pong mechanism based on drm fd to dispatch the BSD command on BDW GT3 Zhao Yakui
2014-04-14 7:22 ` Daniel Vetter
2014-04-14 8:05 ` Zhao Yakui
2014-04-14 8:19 ` Chris Wilson
2014-04-14 8:46 ` Zhao Yakui
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