From mboxrd@z Thu Jan 1 00:00:00 1970 From: Borislav Petkov Subject: Re: 15-rc1: radeon modesetting fails Date: Tue, 15 Apr 2014 16:24:54 +0200 Message-ID: <20140415142454.GA4826@pd.tnic> References: <20140415070204.GA4806@pd.tnic> <534CFBD7.3070604@amd.com> <20140415120740.GA8306@nazgul.tnic> <534D2F6E.1020608@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mail.skyhub.de (mail.skyhub.de [78.46.96.112]) by gabe.freedesktop.org (Postfix) with ESMTP id 4E2B86E235 for ; Tue, 15 Apr 2014 07:24:59 -0700 (PDT) Content-Disposition: inline In-Reply-To: <534D2F6E.1020608@amd.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Christian =?utf-8?B?S8O2bmln?= Cc: Alex Deucher , lkml , Maling list - DRI developers List-Id: dri-devel@lists.freedesktop.org T24gVHVlLCBBcHIgMTUsIDIwMTQgYXQgMDM6MDk6MDJQTSArMDIwMCwgQ2hyaXN0aWFuIEvDtm5p ZyB3cm90ZToKPiA+RG9lcyByZXZlcnRpbmc6Cj4gPmh0dHA6Ly9naXQua2VybmVsLm9yZy9jZ2l0 L2xpbnV4L2tlcm5lbC9naXQvdG9ydmFsZHMvbGludXguZ2l0L2NvbW1pdC8/aWQ9MzIxNjcwMTYw NzZmNzE0ZjBlMzVlMjg3ZmJlYWQ3ZGUwZjFmYjE3OQo+ID5maXggdGhlIGlzc3VlPyAgV2UgbWF5 IG5lZWQgdG8gdHdlYWsgdGhlIHBsbCBwYXJhbWV0ZXJzIGZvciBvbGRlciBhc2ljcy4KPiAKPiBZ ZWFoLCBpbmRlZWQgdGhlIG1vc3QgbGlrZWx5IGNhdXNlLiBQbGVhc2UgcHJvdmlkZSBkbWVzZyBv dXRwdXRzIGNyZWF0ZWQKPiB3aXRoIGRybS5lYnVnPTB4ZSBmb3IgdGhlIG9sZCBhbmQgdGhlIG5l dyBrZXJuZWwuCgpIZXksIEkgZmluYWxseSBoYXogMTUtcmMxKyBydW5uaW5nIGhlcmUuIEFuZCBJ IGNhbiBldmVuIHNlZSBzb21ldGhpbmchCgo6LSkKCk9rLCBzbyBJIHJldmVydGVkIDMyMTY3MDE2 MDc2ZiBvbnRvcCBvZiBDaHJpc3RpYW4ncyBkcm0tZml4ZXMtMy4xNS13aXAKYnJhbmNoIHdoaWNo IGRpZG4ndCBhcHBseSBjbGVhbmx5LiBTbyBJIGVuZGVkIHVwIGZpeGluZyB0aGUgY29uZmxpY3Rz CmFuZCBnb3QgdGhlIHJldmVydCBiZWxvdy4KCldpdGggaXQsIHRoZSBtYWNoaW5lIGJvb3RlZCBm aW5lLCBzbyBpdCBsb29rcyBsaWtlIHRoZSByZXZlcnQgd29ya2VkLgoKQ2hyaXN0aWFuLCBJJ20g c2VuZGluZyBkbWVzZyBvdXRwdXRzIGluIGFub3RoZXIgcHJpdmF0ZSBtYWlsIHRvIHlvdQpndXlz LgoKVGhhbmtzLgoKLS0tCkZyb206IEJvcmlzbGF2IFBldGtvdiA8YnBAc3VzZS5kZT4KRGF0ZTog VHVlLCAxNSBBcHIgMjAxNCAxNjowMDo1OCArMDIwMApTdWJqZWN0OiBbUEFUQ0hdIFJldmVydCAi ZHJtL3JhZGVvbjogcmV3b3JrIGZpbmRpbmcgZGlzcGxheSBQTEwgbnVtYmVycyB2MiIKClRoaXMg cmV2ZXJ0cyBjb21taXQgMzIxNjcwMTYwNzZmNzE0ZjBlMzVlMjg3ZmJlYWQ3ZGUwZjFmYjE3OS4K CkNvbmZsaWN0czoKCWRyaXZlcnMvZ3B1L2RybS9yYWRlb24vcmFkZW9uX2Rpc3BsYXkuYwotLS0K IGRyaXZlcnMvZ3B1L2RybS9yYWRlb24vcmFkZW9uX2Rpc3BsYXkuYyB8IDI0NiArKysrKysrKysr KystLS0tLS0tLS0tLS0tLS0tLS0tLQogMSBmaWxlIGNoYW5nZWQsIDkwIGluc2VydGlvbnMoKyks IDE1NiBkZWxldGlvbnMoLSkKCmRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vcmFkZW9uL3Jh ZGVvbl9kaXNwbGF5LmMgYi9kcml2ZXJzL2dwdS9kcm0vcmFkZW9uL3JhZGVvbl9kaXNwbGF5LmMK aW5kZXggMmY0MjkxMjAzMWFjLi44Mzg5MTkyM2FjMmQgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1 L2RybS9yYWRlb24vcmFkZW9uX2Rpc3BsYXkuYworKysgYi9kcml2ZXJzL2dwdS9kcm0vcmFkZW9u L3JhZGVvbl9kaXNwbGF5LmMKQEAgLTM0LDggKzM0LDYgQEAKICNpbmNsdWRlIDxkcm0vZHJtX2Ny dGNfaGVscGVyLmg+CiAjaW5jbHVkZSA8ZHJtL2RybV9lZGlkLmg+CiAKLSNpbmNsdWRlIDxsaW51 eC9nY2QuaD4KLQogc3RhdGljIHZvaWQgYXZpdm9fY3J0Y19sb2FkX2x1dChzdHJ1Y3QgZHJtX2Ny dGMgKmNydGMpCiB7CiAJc3RydWN0IHJhZGVvbl9jcnRjICpyYWRlb25fY3J0YyA9IHRvX3JhZGVv bl9jcnRjKGNydGMpOwpAQCAtODAyLDU3ICs4MDAsNjYgQEAgaW50IHJhZGVvbl9kZGNfZ2V0X21v ZGVzKHN0cnVjdCByYWRlb25fY29ubmVjdG9yICpyYWRlb25fY29ubmVjdG9yKQogfQogCiAvKiBh dml2byAqLworc3RhdGljIHZvaWQgYXZpdm9fZ2V0X2ZiX2RpdihzdHJ1Y3QgcmFkZW9uX3BsbCAq cGxsLAorCQkJICAgICB1MzIgdGFyZ2V0X2Nsb2NrLAorCQkJICAgICB1MzIgcG9zdF9kaXYsCisJ CQkgICAgIHUzMiByZWZfZGl2LAorCQkJICAgICB1MzIgKmZiX2RpdiwKKwkJCSAgICAgdTMyICpm cmFjX2ZiX2RpdikKK3sKKwl1MzIgdG1wID0gcG9zdF9kaXYgKiByZWZfZGl2OwogCi0vKioKLSAq IGF2aXZvX3JlZHVjZV9yYXRpbyAtIGZyYWN0aW9uYWwgbnVtYmVyIHJlZHVjdGlvbgotICoKLSAq IEBub206IG5vbWluYXRvcgotICogQGRlbjogZGVub21pbmF0b3IKLSAqIEBub21fbWluOiBtaW5p bXVtIHZhbHVlIGZvciBub21pbmF0b3IKLSAqIEBkZW5fbWluOiBtaW5pbXVtIHZhbHVlIGZvciBk ZW5vbWluYXRvcgotICoKLSAqIEZpbmQgdGhlIGdyZWF0ZXN0IGNvbW1vbiBkaXZpc29yIGFuZCBh cHBseSBpdCBvbiBib3RoIG5vbWluYXRvciBhbmQKLSAqIGRlbm9taW5hdG9yLCBidXQgbWFrZSBu b21pbmF0b3IgYW5kIGRlbm9taW5hdG9yIGFyZSBhdCBsZWFzdCBhcyBsYXJnZQotICogYXMgdGhl aXIgbWluaW11bSB2YWx1ZXMuCi0gKi8KLXN0YXRpYyB2b2lkIGF2aXZvX3JlZHVjZV9yYXRpbyh1 bnNpZ25lZCAqbm9tLCB1bnNpZ25lZCAqZGVuLAotCQkJICAgICAgIHVuc2lnbmVkIG5vbV9taW4s IHVuc2lnbmVkIGRlbl9taW4pCisJdG1wICo9IHRhcmdldF9jbG9jazsKKwkqZmJfZGl2ID0gdG1w IC8gcGxsLT5yZWZlcmVuY2VfZnJlcTsKKwkqZnJhY19mYl9kaXYgPSB0bXAgJSBwbGwtPnJlZmVy ZW5jZV9mcmVxOworCisgICAgICAgIGlmICgqZmJfZGl2ID4gcGxsLT5tYXhfZmVlZGJhY2tfZGl2 KQorCQkqZmJfZGl2ID0gcGxsLT5tYXhfZmVlZGJhY2tfZGl2OworICAgICAgICBlbHNlIGlmICgq ZmJfZGl2IDwgcGxsLT5taW5fZmVlZGJhY2tfZGl2KQorICAgICAgICAgICAgICAgICpmYl9kaXYg PSBwbGwtPm1pbl9mZWVkYmFja19kaXY7Cit9CisKK3N0YXRpYyB1MzIgYXZpdm9fZ2V0X3Bvc3Rf ZGl2KHN0cnVjdCByYWRlb25fcGxsICpwbGwsCisJCQkgICAgICB1MzIgdGFyZ2V0X2Nsb2NrKQog ewotCXVuc2lnbmVkIHRtcDsKLQotCS8qIHJlZHVjZSB0aGUgbnVtYmVycyB0byBhIHNpbXBsZXIg cmF0aW8gKi8KLQl0bXAgPSBnY2QoKm5vbSwgKmRlbik7Ci0JKm5vbSAvPSB0bXA7Ci0JKmRlbiAv PSB0bXA7Ci0KLQkvKiBtYWtlIHN1cmUgbm9taW5hdG9yIGlzIGxhcmdlIGVub3VnaCAqLwotICAg ICAgICBpZiAoKm5vbSA8IG5vbV9taW4pIHsKLQkJdG1wID0gKG5vbV9taW4gKyAqbm9tIC0gMSkg LyAqbm9tOwotCQkqbm9tICo9IHRtcDsKLQkJKmRlbiAqPSB0bXA7CisJdTMyIHZjbywgcG9zdF9k aXYsIHRtcDsKKworCWlmIChwbGwtPmZsYWdzICYgUkFERU9OX1BMTF9VU0VfUE9TVF9ESVYpCisJ CXJldHVybiBwbGwtPnBvc3RfZGl2OworCisJaWYgKHBsbC0+ZmxhZ3MgJiBSQURFT05fUExMX1BS RUZFUl9NSU5NX09WRVJfTUFYUCkgeworCQlpZiAocGxsLT5mbGFncyAmIFJBREVPTl9QTExfSVNf TENEKQorCQkJdmNvID0gcGxsLT5sY2RfcGxsX291dF9taW47CisJCWVsc2UKKwkJCXZjbyA9IHBs bC0+cGxsX291dF9taW47CisJfSBlbHNlIHsKKwkJaWYgKHBsbC0+ZmxhZ3MgJiBSQURFT05fUExM X0lTX0xDRCkKKwkJCXZjbyA9IHBsbC0+bGNkX3BsbF9vdXRfbWF4OworCQllbHNlCisJCQl2Y28g PSBwbGwtPnBsbF9vdXRfbWF4OwogCX0KIAotCS8qIG1ha2Ugc3VyZSB0aGUgZGVub21pbmF0b3Ig aXMgbGFyZ2UgZW5vdWdoICovCi0JaWYgKCpkZW4gPCBkZW5fbWluKSB7Ci0JCXRtcCA9IChkZW5f bWluICsgKmRlbiAtIDEpIC8gKmRlbjsKLQkJKm5vbSAqPSB0bXA7Ci0JCSpkZW4gKj0gdG1wOwor CXBvc3RfZGl2ID0gdmNvIC8gdGFyZ2V0X2Nsb2NrOworCXRtcCA9IHZjbyAlIHRhcmdldF9jbG9j azsKKworCWlmIChwbGwtPmZsYWdzICYgUkFERU9OX1BMTF9QUkVGRVJfTUlOTV9PVkVSX01BWFAp IHsKKwkJaWYgKHRtcCkKKwkJCXBvc3RfZGl2Kys7CisJfSBlbHNlIHsKKwkJaWYgKCF0bXApCisJ CQlwb3N0X2Rpdi0tOwogCX0KKworCWlmIChwb3N0X2RpdiA+IHBsbC0+bWF4X3Bvc3RfZGl2KQor CQlwb3N0X2RpdiA9IHBsbC0+bWF4X3Bvc3RfZGl2OworCWVsc2UgaWYgKHBvc3RfZGl2IDwgcGxs LT5taW5fcG9zdF9kaXYpCisJCXBvc3RfZGl2ID0gcGxsLT5taW5fcG9zdF9kaXY7CisKKwlyZXR1 cm4gcG9zdF9kaXY7CiB9CiAKLS8qKgotICogcmFkZW9uX2NvbXB1dGVfcGxsX2F2aXZvIC0gY29t cHV0ZSBQTEwgcGFyYW1hdGVycwotICoKLSAqIEBwbGw6IGluZm9ybWF0aW9uIGFib3V0IHRoZSBQ TEwKLSAqIEBkb3RfY2xvY2tfcDogcmVzdWx0aW5nIHBpeGVsIGNsb2NrCi0gKiBmYl9kaXZfcDog cmVzdWx0aW5nIGZlZWRiYWNrIGRpdmlkZXIKLSAqIGZyYWNfZmJfZGl2X3A6IGZyYWN0aW9uYWwg cGFydCBvZiB0aGUgZmVlZGJhY2sgZGl2aWRlcgotICogcmVmX2Rpdl9wOiByZXN1bHRpbmcgcmVm ZXJlbmNlIGRpdmlkZXIKLSAqIHBvc3RfZGl2X3A6IHJlc3VsdGluZyByZWZlcmVuY2UgZGl2aWRl cgotICoKLSAqIFRyeSB0byBjYWxjdWxhdGUgdGhlIFBMTCBwYXJhbWV0ZXJzIHRvIGdlbmVyYXRl IHRoZSBnaXZlbiBmcmVxdWVuY3k6Ci0gKiBkb3RfY2xvY2sgPSAocmVmX2ZyZXEgKiBmZWVkYmFj a19kaXYpIC8gKHJlZl9kaXYgKiBwb3N0X2RpdikKLSAqLworI2RlZmluZSBNQVhfVE9MRVJBTkNF IDEwCisKIHZvaWQgcmFkZW9uX2NvbXB1dGVfcGxsX2F2aXZvKHN0cnVjdCByYWRlb25fcGxsICpw bGwsCiAJCQkgICAgICB1MzIgZnJlcSwKIAkJCSAgICAgIHUzMiAqZG90X2Nsb2NrX3AsCkBAIC04 NjEsMTI2ICs4NjgsNTMgQEAgdm9pZCByYWRlb25fY29tcHV0ZV9wbGxfYXZpdm8oc3RydWN0IHJh ZGVvbl9wbGwgKnBsbCwKIAkJCSAgICAgIHUzMiAqcmVmX2Rpdl9wLAogCQkJICAgICAgdTMyICpw b3N0X2Rpdl9wKQogewotCXVuc2lnbmVkIGZiX2Rpdl9taW4sIGZiX2Rpdl9tYXgsIGZiX2RpdjsK LQl1bnNpZ25lZCBwb3N0X2Rpdl9taW4sIHBvc3RfZGl2X21heCwgcG9zdF9kaXY7Ci0JdW5zaWdu ZWQgcmVmX2Rpdl9taW4sIHJlZl9kaXZfbWF4LCByZWZfZGl2OwotCXVuc2lnbmVkIHBvc3RfZGl2 X2Jlc3QsIGRpZmZfYmVzdDsKLQl1bnNpZ25lZCBub20sIGRlbiwgdG1wOwotCi0JLyogZGV0ZXJt aW5lIGFsbG93ZWQgZmVlZGJhY2sgZGl2aWRlciByYW5nZSAqLwotCWZiX2Rpdl9taW4gPSBwbGwt Pm1pbl9mZWVkYmFja19kaXY7Ci0JZmJfZGl2X21heCA9IHBsbC0+bWF4X2ZlZWRiYWNrX2RpdjsK Kwl1MzIgdGFyZ2V0X2Nsb2NrID0gZnJlcSAvIDEwOworCXUzMiBwb3N0X2RpdiA9IGF2aXZvX2dl dF9wb3N0X2RpdihwbGwsIHRhcmdldF9jbG9jayk7CisJdTMyIHJlZl9kaXYgPSBwbGwtPm1pbl9y ZWZfZGl2OworCXUzMiBmYl9kaXYgPSAwLCBmcmFjX2ZiX2RpdiA9IDAsIHRtcDsKIAotCWlmIChw bGwtPmZsYWdzICYgUkFERU9OX1BMTF9VU0VfRlJBQ19GQl9ESVYpIHsKLQkJZmJfZGl2X21pbiAq PSAxMDsKLQkJZmJfZGl2X21heCAqPSAxMDsKLQl9Ci0KLQkvKiBkZXRlcm1pbmUgYWxsb3dlZCBy ZWYgZGl2aWRlciByYW5nZSAqLwogCWlmIChwbGwtPmZsYWdzICYgUkFERU9OX1BMTF9VU0VfUkVG X0RJVikKLQkJcmVmX2Rpdl9taW4gPSBwbGwtPnJlZmVyZW5jZV9kaXY7Ci0JZWxzZQotCQlyZWZf ZGl2X21pbiA9IHBsbC0+bWluX3JlZl9kaXY7Ci0JcmVmX2Rpdl9tYXggPSBwbGwtPm1heF9yZWZf ZGl2OworCQlyZWZfZGl2ID0gcGxsLT5yZWZlcmVuY2VfZGl2OwogCi0JLyogZGV0ZXJtaW5lIGFs bG93ZWQgcG9zdCBkaXZpZGVyIHJhbmdlICovCi0JaWYgKHBsbC0+ZmxhZ3MgJiBSQURFT05fUExM X1VTRV9QT1NUX0RJVikgewotCQlwb3N0X2Rpdl9taW4gPSBwbGwtPnBvc3RfZGl2OwotCQlwb3N0 X2Rpdl9tYXggPSBwbGwtPnBvc3RfZGl2OwotCX0gZWxzZSB7Ci0JCXVuc2lnbmVkIHRhcmdldF9j bG9jayA9IGZyZXEgLyAxMDsKLQkJdW5zaWduZWQgdmNvX21pbiwgdmNvX21heDsKLQotCQlpZiAo cGxsLT5mbGFncyAmIFJBREVPTl9QTExfSVNfTENEKSB7Ci0JCQl2Y29fbWluID0gcGxsLT5sY2Rf cGxsX291dF9taW47Ci0JCQl2Y29fbWF4ID0gcGxsLT5sY2RfcGxsX291dF9tYXg7Ci0JCX0gZWxz ZSB7Ci0JCQl2Y29fbWluID0gcGxsLT5wbGxfb3V0X21pbjsKLQkJCXZjb19tYXggPSBwbGwtPnBs bF9vdXRfbWF4OworCWlmIChwbGwtPmZsYWdzICYgUkFERU9OX1BMTF9VU0VfRlJBQ19GQl9ESVYp IHsKKwkJYXZpdm9fZ2V0X2ZiX2RpdihwbGwsIHRhcmdldF9jbG9jaywgcG9zdF9kaXYsIHJlZl9k aXYsICZmYl9kaXYsICZmcmFjX2ZiX2Rpdik7CisJCWZyYWNfZmJfZGl2ID0gKDEwMCAqIGZyYWNf ZmJfZGl2KSAvIHBsbC0+cmVmZXJlbmNlX2ZyZXE7CisJCWlmIChmcmFjX2ZiX2RpdiA+PSA1KSB7 CisJCQlmcmFjX2ZiX2RpdiAtPSA1OworCQkJZnJhY19mYl9kaXYgPSBmcmFjX2ZiX2RpdiAvIDEw OworCQkJZnJhY19mYl9kaXYrKzsKIAkJfQotCi0JCXBvc3RfZGl2X21pbiA9IHZjb19taW4gLyB0 YXJnZXRfY2xvY2s7Ci0JCWlmICgodGFyZ2V0X2Nsb2NrICogcG9zdF9kaXZfbWluKSA8IHZjb19t aW4pCi0JCQkrK3Bvc3RfZGl2X21pbjsKLQkJaWYgKHBvc3RfZGl2X21pbiA8IHBsbC0+bWluX3Bv c3RfZGl2KQotCQkJcG9zdF9kaXZfbWluID0gcGxsLT5taW5fcG9zdF9kaXY7Ci0KLQkJcG9zdF9k aXZfbWF4ID0gdmNvX21heCAvIHRhcmdldF9jbG9jazsKLQkJaWYgKCh0YXJnZXRfY2xvY2sgKiBw b3N0X2Rpdl9tYXgpID4gdmNvX21heCkKLQkJCS0tcG9zdF9kaXZfbWF4OwotCQlpZiAocG9zdF9k aXZfbWF4ID4gcGxsLT5tYXhfcG9zdF9kaXYpCi0JCQlwb3N0X2Rpdl9tYXggPSBwbGwtPm1heF9w b3N0X2RpdjsKLQl9Ci0KLQkvKiByZXByZXNlbnQgdGhlIHNlYXJjaGVkIHJhdGlvIGFzIGZyYWN0 aW9uYWwgbnVtYmVyICovCi0Jbm9tID0gcGxsLT5mbGFncyAmIFJBREVPTl9QTExfVVNFX0ZSQUNf RkJfRElWID8gZnJlcSA6IGZyZXEgLyAxMDsKLQlkZW4gPSBwbGwtPnJlZmVyZW5jZV9mcmVxOwot Ci0JLyogcmVkdWNlIHRoZSBudW1iZXJzIHRvIGEgc2ltcGxlciByYXRpbyAqLwotCWF2aXZvX3Jl ZHVjZV9yYXRpbygmbm9tLCAmZGVuLCBmYl9kaXZfbWluLCBwb3N0X2Rpdl9taW4pOwotCi0JLyog bm93IHNlYXJjaCBmb3IgYSBwb3N0IGRpdmlkZXIgKi8KLQlpZiAocGxsLT5mbGFncyAmIFJBREVP Tl9QTExfUFJFRkVSX01JTk1fT1ZFUl9NQVhQKQotCQlwb3N0X2Rpdl9iZXN0ID0gcG9zdF9kaXZf bWluOwotCWVsc2UKLQkJcG9zdF9kaXZfYmVzdCA9IHBvc3RfZGl2X21heDsKLQlkaWZmX2Jlc3Qg PSB+MDsKLQotCWZvciAocG9zdF9kaXYgPSBwb3N0X2Rpdl9taW47IHBvc3RfZGl2IDw9IHBvc3Rf ZGl2X21heDsgKytwb3N0X2RpdikgewotCQl1bnNpZ25lZCBkaWZmID0gYWJzKGRlbiAtIGRlbiAv IHBvc3RfZGl2ICogcG9zdF9kaXYpOwotCQlpZiAoZGlmZiA8IGRpZmZfYmVzdCB8fCAoZGlmZiA9 PSBkaWZmX2Jlc3QgJiYKLQkJICAgICEocGxsLT5mbGFncyAmIFJBREVPTl9QTExfUFJFRkVSX01J Tk1fT1ZFUl9NQVhQKSkpIHsKLQotCQkJcG9zdF9kaXZfYmVzdCA9IHBvc3RfZGl2OwotCQkJZGlm Zl9iZXN0ID0gZGlmZjsKKwkJaWYgKGZyYWNfZmJfZGl2ID49IDEwKSB7CisJCQlmYl9kaXYrKzsK KwkJCWZyYWNfZmJfZGl2ID0gMDsKIAkJfQotCX0KLQlwb3N0X2RpdiA9IHBvc3RfZGl2X2Jlc3Q7 Ci0KLQkvKiBsaW1pdCByZWZlcmVuY2UgKiBwb3N0IGRpdmlkZXIgdG8gYSBtYXhpbXVtICovCi0J cmVmX2Rpdl9tYXggPSBtaW4oMjEwIC8gcG9zdF9kaXYsIHJlZl9kaXZfbWF4KTsKLQotCS8qIGdl dCBtYXRjaGluZyByZWZlcmVuY2UgYW5kIGZlZWRiYWNrIGRpdmlkZXIgKi8KLQlyZWZfZGl2ID0g bWF4KGRlbiAvIHBvc3RfZGl2LCAxdSk7Ci0JZmJfZGl2ID0gbm9tOwotCi0JLyogd2UncmUgYWxt b3N0IGRvbmUsIGJ1dCByZWZlcmVuY2UgYW5kIGZlZWRiYWNrCi0JICAgZGl2aWRlciBtaWdodCBi ZSB0byBsYXJnZSBub3cgKi8KLQotCXRtcCA9IHJlZl9kaXY7Ci0KLSAgICAgICAgaWYgKGZiX2Rp diA+IGZiX2Rpdl9tYXgpIHsKLQkJcmVmX2RpdiA9IHJlZl9kaXYgKiBmYl9kaXZfbWF4IC8gZmJf ZGl2OwotCQlmYl9kaXYgPSBmYl9kaXZfbWF4OwotCX0KLQotCWlmIChyZWZfZGl2ID4gcmVmX2Rp dl9tYXgpIHsKLQkJcmVmX2RpdiA9IHJlZl9kaXZfbWF4OwotCQlmYl9kaXYgPSBub20gKiByZWZf ZGl2X21heCAvIHRtcDsKLQl9Ci0KLQkvKiByZWR1Y2UgdGhlIG51bWJlcnMgdG8gYSBzaW1wbGVy IHJhdGlvIG9uY2UgbW9yZSAqLwotCS8qIHRoaXMgYWxzbyBtYWtlcyBzdXJlIHRoYXQgdGhlIHJl ZmVyZW5jZSBkaXZpZGVyIGlzIGxhcmdlIGVub3VnaCAqLwotCWF2aXZvX3JlZHVjZV9yYXRpbygm ZmJfZGl2LCAmcmVmX2RpdiwgZmJfZGl2X21pbiwgcmVmX2Rpdl9taW4pOwotCi0JLyogYW5kIGZp bmFsbHkgc2F2ZSB0aGUgcmVzdWx0ICovCi0JaWYgKHBsbC0+ZmxhZ3MgJiBSQURFT05fUExMX1VT RV9GUkFDX0ZCX0RJVikgewotCQkqZmJfZGl2X3AgPSBmYl9kaXYgLyAxMDsKLQkJKmZyYWNfZmJf ZGl2X3AgPSBmYl9kaXYgJSAxMDsKIAl9IGVsc2UgewotCQkqZmJfZGl2X3AgPSBmYl9kaXY7Ci0J CSpmcmFjX2ZiX2Rpdl9wID0gMDsKKwkJd2hpbGUgKHJlZl9kaXYgPD0gcGxsLT5tYXhfcmVmX2Rp dikgeworCQkJYXZpdm9fZ2V0X2ZiX2RpdihwbGwsIHRhcmdldF9jbG9jaywgcG9zdF9kaXYsIHJl Zl9kaXYsCisJCQkJCSAmZmJfZGl2LCAmZnJhY19mYl9kaXYpOworCQkJaWYgKGZyYWNfZmJfZGl2 ID49IChwbGwtPnJlZmVyZW5jZV9mcmVxIC8gMikpCisJCQkJZmJfZGl2Kys7CisJCQlmcmFjX2Zi X2RpdiA9IDA7CisJCQl0bXAgPSAocGxsLT5yZWZlcmVuY2VfZnJlcSAqIGZiX2RpdikgLyAocG9z dF9kaXYgKiByZWZfZGl2KTsKKwkJCXRtcCA9ICh0bXAgKiAxMDAwMCkgLyB0YXJnZXRfY2xvY2s7 CisKKwkJCWlmICh0bXAgPiAoMTAwMDAgKyBNQVhfVE9MRVJBTkNFKSkKKwkJCQlyZWZfZGl2Kys7 CisJCQllbHNlIGlmICh0bXAgPj0gKDEwMDAwIC0gTUFYX1RPTEVSQU5DRSkpCisJCQkJYnJlYWs7 CisJCQllbHNlCisJCQkJcmVmX2RpdisrOworCQl9CiAJfQogCi0JKmRvdF9jbG9ja19wID0gKChw bGwtPnJlZmVyZW5jZV9mcmVxICogKmZiX2Rpdl9wICogMTApICsKLQkJCShwbGwtPnJlZmVyZW5j ZV9mcmVxICogKmZyYWNfZmJfZGl2X3ApKSAvCi0JCSAgICAgICAocmVmX2RpdiAqIHBvc3RfZGl2 ICogMTApOworCSpkb3RfY2xvY2tfcCA9ICgocGxsLT5yZWZlcmVuY2VfZnJlcSAqIGZiX2RpdiAq IDEwKSArIChwbGwtPnJlZmVyZW5jZV9mcmVxICogZnJhY19mYl9kaXYpKSAvCisJCShyZWZfZGl2 ICogcG9zdF9kaXYgKiAxMCk7CisJKmZiX2Rpdl9wID0gZmJfZGl2OworCSpmcmFjX2ZiX2Rpdl9w ID0gZnJhY19mYl9kaXY7CiAJKnJlZl9kaXZfcCA9IHJlZl9kaXY7CiAJKnBvc3RfZGl2X3AgPSBw b3N0X2RpdjsKLQotCURSTV9ERUJVR19LTVMoIiVkIC0gJWQsIHBsbCBkaXZpZGVycyAtIGZiOiAl ZC4lZCByZWY6ICVkLCBwb3N0ICVkXG4iLAotCQkgICAgICBmcmVxLCAqZG90X2Nsb2NrX3AsICpm Yl9kaXZfcCwgKmZyYWNfZmJfZGl2X3AsCi0JCSAgICAgIHJlZl9kaXYsIHBvc3RfZGl2KTsKKwlE Uk1fREVCVUdfS01TKCIlZCwgcGxsIGRpdmlkZXJzIC0gZmI6ICVkLiVkIHJlZjogJWQsIHBvc3Qg JWRcbiIsCisJCSAgICAgICpkb3RfY2xvY2tfcCwgZmJfZGl2LCBmcmFjX2ZiX2RpdiwgcmVmX2Rp diwgcG9zdF9kaXYpOwogfQogCiAvKiBwcmUtYXZpdm8gKi8KLS0gCjEuOS4wCgoKLS0gClJlZ2Fy ZHMvR3J1c3MsCiAgICBCb3Jpcy4KClNlbnQgZnJvbSBhIGZhdCBjcmF0ZSB1bmRlciBteSBkZXNr LiBGb3JtYXR0aW5nIGlzIGZpbmUuCi0tCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fCmRyaS1kZXZlbCBtYWlsaW5nIGxpc3QKZHJpLWRldmVsQGxpc3RzLmZy ZWVkZXNrdG9wLm9yZwpodHRwOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGlu Zm8vZHJpLWRldmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752760AbaDOOZB (ORCPT ); Tue, 15 Apr 2014 10:25:01 -0400 Received: from mail.skyhub.de ([78.46.96.112]:39448 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751037AbaDOOY7 (ORCPT ); Tue, 15 Apr 2014 10:24:59 -0400 Date: Tue, 15 Apr 2014 16:24:54 +0200 From: Borislav Petkov To: Christian =?utf-8?B?S8O2bmln?= Cc: Alex Deucher , Alex Deucher , lkml , Maling list - DRI developers Subject: Re: 15-rc1: radeon modesetting fails Message-ID: <20140415142454.GA4826@pd.tnic> References: <20140415070204.GA4806@pd.tnic> <534CFBD7.3070604@amd.com> <20140415120740.GA8306@nazgul.tnic> <534D2F6E.1020608@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <534D2F6E.1020608@amd.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Apr 15, 2014 at 03:09:02PM +0200, Christian König wrote: > >Does reverting: > >http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=32167016076f714f0e35e287fbead7de0f1fb179 > >fix the issue? We may need to tweak the pll parameters for older asics. > > Yeah, indeed the most likely cause. Please provide dmesg outputs created > with drm.ebug=0xe for the old and the new kernel. Hey, I finally haz 15-rc1+ running here. And I can even see something! :-) Ok, so I reverted 32167016076f ontop of Christian's drm-fixes-3.15-wip branch which didn't apply cleanly. So I ended up fixing the conflicts and got the revert below. With it, the machine booted fine, so it looks like the revert worked. Christian, I'm sending dmesg outputs in another private mail to you guys. Thanks. --- From: Borislav Petkov Date: Tue, 15 Apr 2014 16:00:58 +0200 Subject: [PATCH] Revert "drm/radeon: rework finding display PLL numbers v2" This reverts commit 32167016076f714f0e35e287fbead7de0f1fb179. Conflicts: drivers/gpu/drm/radeon/radeon_display.c --- drivers/gpu/drm/radeon/radeon_display.c | 246 ++++++++++++-------------------- 1 file changed, 90 insertions(+), 156 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index 2f42912031ac..83891923ac2d 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -34,8 +34,6 @@ #include #include -#include - static void avivo_crtc_load_lut(struct drm_crtc *crtc) { struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); @@ -802,57 +800,66 @@ int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) } /* avivo */ +static void avivo_get_fb_div(struct radeon_pll *pll, + u32 target_clock, + u32 post_div, + u32 ref_div, + u32 *fb_div, + u32 *frac_fb_div) +{ + u32 tmp = post_div * ref_div; -/** - * avivo_reduce_ratio - fractional number reduction - * - * @nom: nominator - * @den: denominator - * @nom_min: minimum value for nominator - * @den_min: minimum value for denominator - * - * Find the greatest common divisor and apply it on both nominator and - * denominator, but make nominator and denominator are at least as large - * as their minimum values. - */ -static void avivo_reduce_ratio(unsigned *nom, unsigned *den, - unsigned nom_min, unsigned den_min) + tmp *= target_clock; + *fb_div = tmp / pll->reference_freq; + *frac_fb_div = tmp % pll->reference_freq; + + if (*fb_div > pll->max_feedback_div) + *fb_div = pll->max_feedback_div; + else if (*fb_div < pll->min_feedback_div) + *fb_div = pll->min_feedback_div; +} + +static u32 avivo_get_post_div(struct radeon_pll *pll, + u32 target_clock) { - unsigned tmp; - - /* reduce the numbers to a simpler ratio */ - tmp = gcd(*nom, *den); - *nom /= tmp; - *den /= tmp; - - /* make sure nominator is large enough */ - if (*nom < nom_min) { - tmp = (nom_min + *nom - 1) / *nom; - *nom *= tmp; - *den *= tmp; + u32 vco, post_div, tmp; + + if (pll->flags & RADEON_PLL_USE_POST_DIV) + return pll->post_div; + + if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) { + if (pll->flags & RADEON_PLL_IS_LCD) + vco = pll->lcd_pll_out_min; + else + vco = pll->pll_out_min; + } else { + if (pll->flags & RADEON_PLL_IS_LCD) + vco = pll->lcd_pll_out_max; + else + vco = pll->pll_out_max; } - /* make sure the denominator is large enough */ - if (*den < den_min) { - tmp = (den_min + *den - 1) / *den; - *nom *= tmp; - *den *= tmp; + post_div = vco / target_clock; + tmp = vco % target_clock; + + if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) { + if (tmp) + post_div++; + } else { + if (!tmp) + post_div--; } + + if (post_div > pll->max_post_div) + post_div = pll->max_post_div; + else if (post_div < pll->min_post_div) + post_div = pll->min_post_div; + + return post_div; } -/** - * radeon_compute_pll_avivo - compute PLL paramaters - * - * @pll: information about the PLL - * @dot_clock_p: resulting pixel clock - * fb_div_p: resulting feedback divider - * frac_fb_div_p: fractional part of the feedback divider - * ref_div_p: resulting reference divider - * post_div_p: resulting reference divider - * - * Try to calculate the PLL parameters to generate the given frequency: - * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div) - */ +#define MAX_TOLERANCE 10 + void radeon_compute_pll_avivo(struct radeon_pll *pll, u32 freq, u32 *dot_clock_p, @@ -861,126 +868,53 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll, u32 *ref_div_p, u32 *post_div_p) { - unsigned fb_div_min, fb_div_max, fb_div; - unsigned post_div_min, post_div_max, post_div; - unsigned ref_div_min, ref_div_max, ref_div; - unsigned post_div_best, diff_best; - unsigned nom, den, tmp; - - /* determine allowed feedback divider range */ - fb_div_min = pll->min_feedback_div; - fb_div_max = pll->max_feedback_div; + u32 target_clock = freq / 10; + u32 post_div = avivo_get_post_div(pll, target_clock); + u32 ref_div = pll->min_ref_div; + u32 fb_div = 0, frac_fb_div = 0, tmp; - if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { - fb_div_min *= 10; - fb_div_max *= 10; - } - - /* determine allowed ref divider range */ if (pll->flags & RADEON_PLL_USE_REF_DIV) - ref_div_min = pll->reference_div; - else - ref_div_min = pll->min_ref_div; - ref_div_max = pll->max_ref_div; + ref_div = pll->reference_div; - /* determine allowed post divider range */ - if (pll->flags & RADEON_PLL_USE_POST_DIV) { - post_div_min = pll->post_div; - post_div_max = pll->post_div; - } else { - unsigned target_clock = freq / 10; - unsigned vco_min, vco_max; - - if (pll->flags & RADEON_PLL_IS_LCD) { - vco_min = pll->lcd_pll_out_min; - vco_max = pll->lcd_pll_out_max; - } else { - vco_min = pll->pll_out_min; - vco_max = pll->pll_out_max; + if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { + avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div); + frac_fb_div = (100 * frac_fb_div) / pll->reference_freq; + if (frac_fb_div >= 5) { + frac_fb_div -= 5; + frac_fb_div = frac_fb_div / 10; + frac_fb_div++; } - - post_div_min = vco_min / target_clock; - if ((target_clock * post_div_min) < vco_min) - ++post_div_min; - if (post_div_min < pll->min_post_div) - post_div_min = pll->min_post_div; - - post_div_max = vco_max / target_clock; - if ((target_clock * post_div_max) > vco_max) - --post_div_max; - if (post_div_max > pll->max_post_div) - post_div_max = pll->max_post_div; - } - - /* represent the searched ratio as fractional number */ - nom = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? freq : freq / 10; - den = pll->reference_freq; - - /* reduce the numbers to a simpler ratio */ - avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min); - - /* now search for a post divider */ - if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) - post_div_best = post_div_min; - else - post_div_best = post_div_max; - diff_best = ~0; - - for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { - unsigned diff = abs(den - den / post_div * post_div); - if (diff < diff_best || (diff == diff_best && - !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) { - - post_div_best = post_div; - diff_best = diff; + if (frac_fb_div >= 10) { + fb_div++; + frac_fb_div = 0; } - } - post_div = post_div_best; - - /* limit reference * post divider to a maximum */ - ref_div_max = min(210 / post_div, ref_div_max); - - /* get matching reference and feedback divider */ - ref_div = max(den / post_div, 1u); - fb_div = nom; - - /* we're almost done, but reference and feedback - divider might be to large now */ - - tmp = ref_div; - - if (fb_div > fb_div_max) { - ref_div = ref_div * fb_div_max / fb_div; - fb_div = fb_div_max; - } - - if (ref_div > ref_div_max) { - ref_div = ref_div_max; - fb_div = nom * ref_div_max / tmp; - } - - /* reduce the numbers to a simpler ratio once more */ - /* this also makes sure that the reference divider is large enough */ - avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); - - /* and finally save the result */ - if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { - *fb_div_p = fb_div / 10; - *frac_fb_div_p = fb_div % 10; } else { - *fb_div_p = fb_div; - *frac_fb_div_p = 0; + while (ref_div <= pll->max_ref_div) { + avivo_get_fb_div(pll, target_clock, post_div, ref_div, + &fb_div, &frac_fb_div); + if (frac_fb_div >= (pll->reference_freq / 2)) + fb_div++; + frac_fb_div = 0; + tmp = (pll->reference_freq * fb_div) / (post_div * ref_div); + tmp = (tmp * 10000) / target_clock; + + if (tmp > (10000 + MAX_TOLERANCE)) + ref_div++; + else if (tmp >= (10000 - MAX_TOLERANCE)) + break; + else + ref_div++; + } } - *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) + - (pll->reference_freq * *frac_fb_div_p)) / - (ref_div * post_div * 10); + *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) / + (ref_div * post_div * 10); + *fb_div_p = fb_div; + *frac_fb_div_p = frac_fb_div; *ref_div_p = ref_div; *post_div_p = post_div; - - DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n", - freq, *dot_clock_p, *fb_div_p, *frac_fb_div_p, - ref_div, post_div); + DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n", + *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div); } /* pre-avivo */ -- 1.9.0 -- Regards/Gruss, Boris. Sent from a fat crate under my desk. Formatting is fine. --