From: Borislav Petkov <bp@suse.de>
To: Myron Stowe <myron.stowe@redhat.com>
Cc: bhelgaas@google.com, linux-pci@vger.kernel.org,
suravee.suthikulpanit@amd.com, aravind.gopalakrishnan@amd.com,
kim.naru@amd.com, daniel@numascale.com, tglx@linutronix.de,
mingo@redhat.com, hpa@zytor.com, x86@kernel.org, bp@suse.de,
sp@numascale.com, linux-acpi@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 2/5] x86/PCI: Support additional MMIO range capabilities
Date: Sun, 20 Apr 2014 09:59:37 +0200 [thread overview]
Message-ID: <20140420075936.GA19672@pd.tnic> (raw)
In-Reply-To: <20140419135219.GC8109@pd.tnic>
Drop Andreas' old email address from CC as it keeps bouncing.
On Sat, Apr 19, 2014 at 03:52:20PM +0200, Borislav Petkov wrote:
> > -static void __init pci_enable_pci_io_ecs(void)
> > +static void __init pci_enable_pci_io_ecs(u8 bus, u8 slot)
> > {
> > #ifdef CONFIG_AMD_NB
> > unsigned int i, n;
> > + u8 limit;
> >
> > for (n = i = 0; !n && amd_nb_bus_dev_ranges[i].dev_limit; ++i) {
> > - u8 bus = amd_nb_bus_dev_ranges[i].bus;
> > - u8 slot = amd_nb_bus_dev_ranges[i].dev_base;
> > - u8 limit = amd_nb_bus_dev_ranges[i].dev_limit;
> > + /* Try matching for the bus range */
> > + if ((bus != amd_nb_bus_dev_ranges[i].bus) ||
> > + (slot != amd_nb_bus_dev_ranges[i].dev_base))
> > + continue;
> > +
> > + limit = amd_nb_bus_dev_ranges[i].dev_limit;
> >
> > + /* Setup all northbridges within the range */
> > for (; slot < limit; ++slot) {
> > u32 val = read_pci_config(bus, slot, 3, 0);
> > -
> > - if (!early_is_amd_nb(val))
> > + if (!val)
> > continue;
> >
> > val = read_pci_config(bus, slot, 3, 0x8c);
> > @@ -375,13 +457,14 @@ static void __init pci_enable_pci_io_ecs(void)
> > val |= ENABLE_CF8_EXT_CFG >> 32;
>
> What a fun shifting!
>
> Maybe you should do
>
> #define ENABLE_CF8_EXT_CFG BIT(46 - 32)
>
> to show exactly what you mean and how the bit is defined in MSR NB_CFG1
> and also show how the high 32-bits are mapped into F3x8c, while at it.
>
> And then you can drop the shifting at the call site.
Ok, I see another fun with this ECS enabling:
There's a enable_pci_io_ecs() which enables ECS through the NB_CFG MSR
which is called as part of the notifier *and* there's a PCI write to
that same bit in pci_enable_pci_io_ecs() which iterates over all NBs.
So, AFAICT, we do it twice and the second time is not needed. Which
means, you probably can drop pci_enable_pci_io_ecs() completely and use
solely the notifier?
Yes, no?
--
Regards/Gruss,
Boris.
Sent from a fat crate under my desk. Formatting is fine.
--
next prev parent reply other threads:[~2014-04-20 7:59 UTC|newest]
Thread overview: 69+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-03-05 21:06 [PATCH 0/3] amd/pci: Add AMD hostbridge supports for newer AMD systems suravee.suthikulpanit
2014-03-05 21:06 ` [PATCH 1/3] amd/pci: Add supports for generic AMD hostbridges suravee.suthikulpanit
2014-03-05 21:06 ` [PATCH 2/3] amd/pci: Support additional MMIO ranges capabilities suravee.suthikulpanit
2014-03-20 17:33 ` Bjorn Helgaas
2014-03-05 21:06 ` [PATCH 3/3] amd/pci: Miscellaneous code clean up for early_fillup_mp_bus_info suravee.suthikulpanit
2014-03-05 21:24 ` [PATCH 0/3] amd/pci: Add AMD hostbridge supports for newer AMD systems Bjorn Helgaas
2014-03-06 2:13 ` Suravee Suthikulanit
2014-03-06 2:13 ` Suravee Suthikulanit
2014-03-06 6:30 ` Suravee Suthikulpanit
2014-03-06 6:30 ` Suravee Suthikulpanit
2014-03-06 17:40 ` Bjorn Helgaas
2014-03-06 20:03 ` Suravee Suthikulpanit
2014-03-06 20:03 ` Suravee Suthikulpanit
2014-03-11 18:12 ` Bjorn Helgaas
2014-03-12 21:13 ` Bjorn Helgaas
2014-03-13 1:30 ` Myron Stowe
2014-03-14 2:06 ` Suravee Suthikulpanit
2014-03-14 2:06 ` Suravee Suthikulpanit
2014-03-17 17:18 ` Bjorn Helgaas
2014-03-20 17:42 ` Bjorn Helgaas
2014-04-19 2:53 ` [PATCH v2 0/5] x86/PCI: Add AMD hostbridge support " Myron Stowe
2014-04-19 2:53 ` [PATCH v2 1/5] x86/PCI: Add support for generic AMD hostbridges Myron Stowe
2014-04-19 11:31 ` Borislav Petkov
2014-04-28 21:10 ` Myron Stowe
2014-04-19 2:53 ` [PATCH v2 2/5] x86/PCI: Support additional MMIO range capabilities Myron Stowe
2014-04-19 13:52 ` Borislav Petkov
2014-04-20 7:59 ` Borislav Petkov [this message]
2014-04-25 22:24 ` Myron Stowe
2014-04-26 9:10 ` Borislav Petkov
2014-04-28 20:50 ` Bjorn Helgaas
2014-04-28 21:40 ` Borislav Petkov
2014-04-28 21:40 ` Borislav Petkov
2014-04-29 7:33 ` Andreas Herrmann
2014-04-29 10:20 ` Borislav Petkov
2014-04-29 13:07 ` Steffen Persvold
2014-04-29 15:16 ` Suravee Suthikulanit
2014-04-29 15:16 ` Suravee Suthikulanit
2014-04-29 19:14 ` Borislav Petkov
2014-04-29 21:40 ` Myron Stowe
2014-04-30 7:00 ` Robert Richter
2014-04-30 7:50 ` Suravee Suthikulpanit
2014-04-30 7:50 ` Suravee Suthikulpanit
2014-04-30 9:51 ` Robert Richter
2014-04-30 23:03 ` Myron Stowe
2014-04-29 11:19 ` Robert Richter
2014-04-29 7:06 ` Jan Beulich
2014-04-29 7:06 ` Jan Beulich
2014-04-29 3:04 ` Suravee Suthikulanit
2014-04-29 3:04 ` Suravee Suthikulanit
2014-04-28 21:19 ` Myron Stowe
2014-04-29 2:47 ` Suravee Suthikulanit
2014-04-29 2:47 ` Suravee Suthikulanit
2014-04-29 17:17 ` Robert Richter
2014-04-30 6:41 ` Robert Richter
2014-04-19 2:53 ` [PATCH v2 3/5] x86/PCI: Miscellaneous code clean up for early_fillup_mp_bus_info Myron Stowe
2014-04-20 8:02 ` Borislav Petkov
2014-04-28 21:21 ` Myron Stowe
2014-04-19 2:53 ` [PATCH v2 4/5] ACPI/PCI: Warn if we have to "guess" host bridge node information Myron Stowe
2014-04-20 10:21 ` Borislav Petkov
2014-04-28 21:24 ` Myron Stowe
2014-04-29 19:16 ` Borislav Petkov
2014-04-19 2:53 ` [PATCH v2 5/5] PCI: Remove redundant 'quirk_amd_nb_node' Myron Stowe
2014-04-20 10:54 ` Borislav Petkov
2014-04-20 13:44 ` Myron Stowe
2014-04-21 16:53 ` Daniel J Blueman
2014-04-29 2:02 ` Suravee Suthikulanit
2014-04-29 2:02 ` Suravee Suthikulanit
2014-04-29 19:29 ` Bjorn Helgaas
2014-04-28 21:28 ` Myron Stowe
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