diff for duplicates of <20140422115716.GP30677@intel.com> diff --git a/a/1.txt b/N1/1.txt index f4de655..bea295b 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,6 +1,6 @@ On Fri, Apr 18, 2014 at 05:30:54PM +0100, Mark Brown wrote: > On Fri, Apr 18, 2014 at 12:26:07AM +0800, Chew Chiau Ee wrote: -> > From: Chew, Chiau Ee <chiau.ee.chew-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> +> > From: Chew, Chiau Ee <chiau.ee.chew@intel.com> > > > > Intel BayTrail PCI mode LPSS devices inclusive of SPI do not rely > > on common clock framework. Thus, this patch allows the PCI mode @@ -21,7 +21,3 @@ enumerated devices? Surely we don't want to have board files to do this. In ACPI mode, we do it in drivers/acpi/acpi_lpss.c but not sure where we could do that in PCI code. --- -To unsubscribe from this list: send the line "unsubscribe linux-spi" in -the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org -More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index a807006..a12dd5c 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,22 +1,21 @@ "ref\01397751967-20250-1-git-send-email-chiau.ee.chew@intel.com\0" "ref\01397751967-20250-3-git-send-email-chiau.ee.chew@intel.com\0" "ref\020140418163054.GH12304@sirena.org.uk\0" - "ref\020140418163054.GH12304-GFdadSzt00ze9xe1eoZjHA@public.gmane.org\0" - "From\0Mika Westerberg <mika.westerberg-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>\0" + "From\0Mika Westerberg <mika.westerberg@linux.intel.com>\0" "Subject\0Re: [PATCH 2/2] spi/pxa2xx-pci: Pass host clock rate info from PCI glue layer\0" "Date\0Tue, 22 Apr 2014 14:57:17 +0300\0" - "To\0Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>\0" - "Cc\0Chew Chiau Ee <chiau.ee.chew-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>" - Eric Miao <eric.y.miao-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> - Russell King <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org> - Haojian Zhuang <haojian.zhuang-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> - linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - " linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" + "To\0Mark Brown <broonie@kernel.org>\0" + "Cc\0Chew Chiau Ee <chiau.ee.chew@intel.com>" + Eric Miao <eric.y.miao@gmail.com> + Russell King <linux@arm.linux.org.uk> + Haojian Zhuang <haojian.zhuang@gmail.com> + linux-spi@vger.kernel.org + " linux-kernel@vger.kernel.org\0" "\00:1\0" "b\0" "On Fri, Apr 18, 2014 at 05:30:54PM +0100, Mark Brown wrote:\n" "> On Fri, Apr 18, 2014 at 12:26:07AM +0800, Chew Chiau Ee wrote:\n" - "> > From: Chew, Chiau Ee <chiau.ee.chew-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>\n" + "> > From: Chew, Chiau Ee <chiau.ee.chew@intel.com>\n" "> > \n" "> > Intel BayTrail PCI mode LPSS devices inclusive of SPI do not rely\n" "> > on common clock framework. Thus, this patch allows the PCI mode\n" @@ -36,10 +35,6 @@ "enumerated devices? Surely we don't want to have board files to do this.\n" "\n" "In ACPI mode, we do it in drivers/acpi/acpi_lpss.c but not sure where we\n" - "could do that in PCI code.\n" - "--\n" - "To unsubscribe from this list: send the line \"unsubscribe linux-spi\" in\n" - "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" - More majordomo info at http://vger.kernel.org/majordomo-info.html + could do that in PCI code. -eff23cf13f212d0dc72b85276cf774ca7f27086df3b83230ce18ac3d583d3d9c +f51d2b9fc881a793c25fd175204e1618fd8ae5804b6e1b0346d96e6d7025cc4a
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