From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paul Mackerras Date: Wed, 30 Apr 2014 22:12:59 +0000 Subject: Re: [PATCH 1/6] KVM: PPC: Book3S PR: Ignore PMU SPRs Message-Id: <20140430221259.GD9671@iris.ozlabs.ibm.com> List-Id: References: <1398788262-3307-1-git-send-email-agraf@suse.de> <1398788262-3307-2-git-send-email-agraf@suse.de> In-Reply-To: <1398788262-3307-2-git-send-email-agraf@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: Alexander Graf Cc: kvm-ppc@vger.kernel.org, kvm@vger.kernel.org On Tue, Apr 29, 2014 at 06:17:37PM +0200, Alexander Graf wrote: > When we expose a POWER8 CPU into the guest, it will start accessing PMU SPRs > that we don't emulate. Just ignore accesses to them. > > Signed-off-by: Alexander Graf This patch is OK as it stands, but in fact the architecture says that kernel accesses to unimplemented SPRs are mostly supposed to be no-ops rather than causing a trap (mostly = excluding mtspr to 0 or mfspr from 0, 4, 5 or 6). I have a patch to implement that, which I'll post. Paul. From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paul Mackerras Subject: Re: [PATCH 1/6] KVM: PPC: Book3S PR: Ignore PMU SPRs Date: Wed, 30 Apr 2014 17:12:59 -0500 Message-ID: <20140430221259.GD9671@iris.ozlabs.ibm.com> References: <1398788262-3307-1-git-send-email-agraf@suse.de> <1398788262-3307-2-git-send-email-agraf@suse.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: kvm-ppc@vger.kernel.org, kvm@vger.kernel.org To: Alexander Graf Return-path: Content-Disposition: inline In-Reply-To: <1398788262-3307-2-git-send-email-agraf@suse.de> Sender: kvm-ppc-owner@vger.kernel.org List-Id: kvm.vger.kernel.org On Tue, Apr 29, 2014 at 06:17:37PM +0200, Alexander Graf wrote: > When we expose a POWER8 CPU into the guest, it will start accessing PMU SPRs > that we don't emulate. Just ignore accesses to them. > > Signed-off-by: Alexander Graf This patch is OK as it stands, but in fact the architecture says that kernel accesses to unimplemented SPRs are mostly supposed to be no-ops rather than causing a trap (mostly == excluding mtspr to 0 or mfspr from 0, 4, 5 or 6). I have a patch to implement that, which I'll post. Paul.