From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] ARM: mm: Add workaround for erratum 763126
Date: Thu, 8 May 2014 18:38:53 +0100 [thread overview]
Message-ID: <20140508173853.GG8981@arm.com> (raw)
In-Reply-To: <CAD=FV=XeYdgqk3-CpS2NNXFAnn+uGDC6844d-L6vfS=SYEuw-Q@mail.gmail.com>
Hi guys,
On Thu, May 08, 2014 at 05:57:03PM +0100, Doug Anderson wrote:
> On Wed, May 7, 2014 at 10:55 PM, Arjun.K.V <arjun.kv@samsung.com> wrote:
> > From: "Arjun.K.V" <arjun.kv@samsung.com>
> >
> > Three processor exclusive access livelock.
> > In a system with three or more coherent masters that all use
> > the ldrex/strex synchronization primitives to access a semaphore
> > in coherent cacheable memory, there is a possibility of a
> > livelock condition where two masters continuously attempt
> > and fail to get the lock while the third master
> > continuously reads the lock.
Tentative NAK. You're paraphrasing the bug to make it sound worse than it
is -- whilst two of the cores need to be in a ldrex/strex loop, the third
needs to be issuing snoops from a normal load (to get the line into a shared
state). Please can you point me at the code in Linux which is triggering
this issue?
Cheers,
Will
next prev parent reply other threads:[~2014-05-08 17:38 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-08 5:55 [PATCH] ARM: mm: Add workaround for erratum 763126 Arjun.K.V
2014-05-08 16:57 ` Doug Anderson
2014-05-08 17:38 ` Will Deacon [this message]
2014-05-08 17:57 ` Doug Anderson
2014-05-08 18:05 ` Will Deacon
[not found] ` <CAFY15YHPSLMh6iA1PQHjsneL_Kxarc0xL5uJ7_px71cbmJbrgQ@mail.gmail.com>
2014-05-09 14:44 ` Catalin Marinas
2014-05-12 16:36 ` Doug Anderson
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