From mboxrd@z Thu Jan 1 00:00:00 1970 From: alexandre.belloni@free-electrons.com (Alexandre Belloni) Date: Mon, 12 May 2014 11:48:36 +0200 Subject: [PATCH v2 1/2] ARM: at91: add PWM pinctrl to SAMA5D3 In-Reply-To: <1399887854-12612-1-git-send-email-nicolas.ferre@atmel.com> References: <1399887854-12612-1-git-send-email-nicolas.ferre@atmel.com> Message-ID: <20140512094835.GB29318@piout.net> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 12/05/2014 at 11:44:14 +0200, Nicolas Ferre wrote : > Signed-off-by: Nicolas Ferre Acked-by: Alexandre Belloni > --- > v1 -> v2: - removed useless comment part, kept the "conflicts with..." part > - grouped "high" and "low" signal definitions together for each > channel > > arch/arm/boot/dts/sama5d3.dtsi | 78 ++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 78 insertions(+) > > diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi > index 9caa06b3641e..e08da17e1890 100644 > --- a/arch/arm/boot/dts/sama5d3.dtsi > +++ b/arch/arm/boot/dts/sama5d3.dtsi > @@ -583,6 +583,84 @@ > }; > }; > > + pwm0 { > + pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 { > + atmel,pins = > + ; /* conflicts with ISI_D4 and LCDDAT20 */ > + }; > + pinctrl_pwm0_pwmh0_1: pwm0_pwmh0-1 { > + atmel,pins = > + ; /* conflicts with GTX0 */ > + }; > + pinctrl_pwm0_pwml0_0: pwm0_pwml0-0 { > + atmel,pins = > + ; /* conflicts with ISI_D5 and LCDDAT21 */ > + }; > + pinctrl_pwm0_pwml0_1: pwm0_pwml0-1 { > + atmel,pins = > + ; /* conflicts with GTX1 */ > + }; > + > + pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 { > + atmel,pins = > + ; /* conflicts with ISI_D6 and LCDDAT22 */ > + }; > + pinctrl_pwm0_pwmh1_1: pwm0_pwmh1-1 { > + atmel,pins = > + ; /* conflicts with GRX0 */ > + }; > + pinctrl_pwm0_pwmh1_2: pwm0_pwmh1-2 { > + atmel,pins = > + ; /* conflicts with G125CKO and RTS1 */ > + }; > + pinctrl_pwm0_pwml1_0: pwm0_pwml1-0 { > + atmel,pins = > + ; /* conflicts with ISI_D7 and LCDDAT23 */ > + }; > + pinctrl_pwm0_pwml1_1: pwm0_pwml1-1 { > + atmel,pins = > + ; /* conflicts with GRX1 */ > + }; > + pinctrl_pwm0_pwml1_2: pwm0_pwml1-2 { > + atmel,pins = > + ; /* conflicts with IRQ */ > + }; > + > + pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 { > + atmel,pins = > + ; /* conflicts with GTXCK */ > + }; > + pinctrl_pwm0_pwmh2_1: pwm0_pwmh2-1 { > + atmel,pins = > + ; /* conflicts with MCI0_DA4 and TIOA0 */ > + }; > + pinctrl_pwm0_pwml2_0: pwm0_pwml2-0 { > + atmel,pins = > + ; /* conflicts with GTXEN */ > + }; > + pinctrl_pwm0_pwml2_1: pwm0_pwml2-1 { > + atmel,pins = > + ; /* conflicts with MCI0_DA5 and TIOB0 */ > + }; > + > + pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 { > + atmel,pins = > + ; /* conflicts with GRXDV */ > + }; > + pinctrl_pwm0_pwmh3_1: pwm0_pwmh3-1 { > + atmel,pins = > + ; /* conflicts with MCI0_DA6 and TCLK0 */ > + }; > + pinctrl_pwm0_pwml3_0: pwm0_pwml3-0 { > + atmel,pins = > + ; /* conflicts with GRXER */ > + }; > + pinctrl_pwm0_pwml3_1: pwm0_pwml3-1 { > + atmel,pins = > + ; /* conflicts with MCI0_DA7 */ > + }; > + }; > + > spi0 { > pinctrl_spi0: spi0-0 { > atmel,pins = > -- > 1.8.2.2 > -- Alexandre Belloni, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755865AbaELJsl (ORCPT ); Mon, 12 May 2014 05:48:41 -0400 Received: from top.free-electrons.com ([176.31.233.9]:57373 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1755055AbaELJsj convert rfc822-to-8bit (ORCPT ); Mon, 12 May 2014 05:48:39 -0400 Date: Mon, 12 May 2014 11:48:36 +0200 From: Alexandre Belloni To: Nicolas Ferre Cc: linux-arm-kernel@lists.infradead.org, Boris BREZILLON , Jean-Christophe PLAGNIOL-VILLARD , linux-kernel@vger.kernel.org, Bo Shen Subject: Re: [PATCH v2 1/2] ARM: at91: add PWM pinctrl to SAMA5D3 Message-ID: <20140512094835.GB29318@piout.net> References: <1399887854-12612-1-git-send-email-nicolas.ferre@atmel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: 8BIT In-Reply-To: <1399887854-12612-1-git-send-email-nicolas.ferre@atmel.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/05/2014 at 11:44:14 +0200, Nicolas Ferre wrote : > Signed-off-by: Nicolas Ferre Acked-by: Alexandre Belloni > --- > v1 -> v2: - removed useless comment part, kept the "conflicts with..." part > - grouped "high" and "low" signal definitions together for each > channel > > arch/arm/boot/dts/sama5d3.dtsi | 78 ++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 78 insertions(+) > > diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi > index 9caa06b3641e..e08da17e1890 100644 > --- a/arch/arm/boot/dts/sama5d3.dtsi > +++ b/arch/arm/boot/dts/sama5d3.dtsi > @@ -583,6 +583,84 @@ > }; > }; > > + pwm0 { > + pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 { > + atmel,pins = > + ; /* conflicts with ISI_D4 and LCDDAT20 */ > + }; > + pinctrl_pwm0_pwmh0_1: pwm0_pwmh0-1 { > + atmel,pins = > + ; /* conflicts with GTX0 */ > + }; > + pinctrl_pwm0_pwml0_0: pwm0_pwml0-0 { > + atmel,pins = > + ; /* conflicts with ISI_D5 and LCDDAT21 */ > + }; > + pinctrl_pwm0_pwml0_1: pwm0_pwml0-1 { > + atmel,pins = > + ; /* conflicts with GTX1 */ > + }; > + > + pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 { > + atmel,pins = > + ; /* conflicts with ISI_D6 and LCDDAT22 */ > + }; > + pinctrl_pwm0_pwmh1_1: pwm0_pwmh1-1 { > + atmel,pins = > + ; /* conflicts with GRX0 */ > + }; > + pinctrl_pwm0_pwmh1_2: pwm0_pwmh1-2 { > + atmel,pins = > + ; /* conflicts with G125CKO and RTS1 */ > + }; > + pinctrl_pwm0_pwml1_0: pwm0_pwml1-0 { > + atmel,pins = > + ; /* conflicts with ISI_D7 and LCDDAT23 */ > + }; > + pinctrl_pwm0_pwml1_1: pwm0_pwml1-1 { > + atmel,pins = > + ; /* conflicts with GRX1 */ > + }; > + pinctrl_pwm0_pwml1_2: pwm0_pwml1-2 { > + atmel,pins = > + ; /* conflicts with IRQ */ > + }; > + > + pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 { > + atmel,pins = > + ; /* conflicts with GTXCK */ > + }; > + pinctrl_pwm0_pwmh2_1: pwm0_pwmh2-1 { > + atmel,pins = > + ; /* conflicts with MCI0_DA4 and TIOA0 */ > + }; > + pinctrl_pwm0_pwml2_0: pwm0_pwml2-0 { > + atmel,pins = > + ; /* conflicts with GTXEN */ > + }; > + pinctrl_pwm0_pwml2_1: pwm0_pwml2-1 { > + atmel,pins = > + ; /* conflicts with MCI0_DA5 and TIOB0 */ > + }; > + > + pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 { > + atmel,pins = > + ; /* conflicts with GRXDV */ > + }; > + pinctrl_pwm0_pwmh3_1: pwm0_pwmh3-1 { > + atmel,pins = > + ; /* conflicts with MCI0_DA6 and TCLK0 */ > + }; > + pinctrl_pwm0_pwml3_0: pwm0_pwml3-0 { > + atmel,pins = > + ; /* conflicts with GRXER */ > + }; > + pinctrl_pwm0_pwml3_1: pwm0_pwml3-1 { > + atmel,pins = > + ; /* conflicts with MCI0_DA7 */ > + }; > + }; > + > spi0 { > pinctrl_spi0: spi0-0 { > atmel,pins = > -- > 1.8.2.2 > -- Alexandre Belloni, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com