From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 4/5] drm/i915: Use ilk_wm_max_level() in latency debugfs files Date: Tue, 13 May 2014 19:30:50 +0300 Message-ID: <20140513163050.GH18465@intel.com> References: <1399991428-32763-1-git-send-email-damien.lespiau@intel.com> <1399991428-32763-5-git-send-email-damien.lespiau@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 7EE646EB44 for ; Tue, 13 May 2014 09:30:54 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1399991428-32763-5-git-send-email-damien.lespiau@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Damien Lespiau Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, May 13, 2014 at 03:30:27PM +0100, Damien Lespiau wrote: > Signed-off-by: Damien Lespiau > --- > drivers/gpu/drm/i915/i915_debugfs.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i= 915_debugfs.c > index 18b3565..6801987 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -3084,7 +3084,7 @@ static const struct file_operations i915_display_cr= c_ctl_fops =3D { > static void wm_latency_show(struct seq_file *m, const uint16_t wm[5]) > { > struct drm_device *dev =3D m->private; > - int num_levels =3D IS_HASWELL(dev) || IS_BROADWELL(dev) ? 5 : 4; > + int num_levels =3D ilk_wm_max_level(dev) + 1; > int level; > = > drm_modeset_lock_all(dev); > @@ -3167,7 +3167,7 @@ static ssize_t wm_latency_write(struct file *file, = const char __user *ubuf, > struct seq_file *m =3D file->private_data; > struct drm_device *dev =3D m->private; > uint16_t new[5] =3D { 0 }; > - int num_levels =3D IS_HASWELL(dev) || IS_BROADWELL(dev) ? 5 : 4; > + int num_levels =3D ilk_wm_max_level(dev) + 1; One idea that has been rattling in my head would be to introduce dev_priv->wm.max_level or some such thing that would be computed dynamically like so: dev_priv->wm.max_level =3D min(hw_max, last_level_with_valid_latency_value); This way we could actually disable some of the deeper levels without worrying that the watermark code will encounter a zero latency value somewhere. We could even do other crazy things like trying out LP3 on ILK ;) But that's a bit orthogonal, and even then this patch does make sense. For patches 3-5: Reviewed-by: Ville Syrj=E4l=E4 I'll let someone else bikeshed the for_each_crtc macros. > int level; > int ret; > char tmp[32]; > -- = > 1.8.3.1 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC