From: catalin.marinas@arm.com (Catalin Marinas)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCHv5 3/4] ARM: mvebu: implement L2/PCIe deadlock workaround
Date: Mon, 19 May 2014 11:08:29 +0100 [thread overview]
Message-ID: <20140519100829.GE5113@arm.com> (raw)
In-Reply-To: <1400487234-4501-4-git-send-email-thomas.petazzoni@free-electrons.com>
On Mon, May 19, 2014 at 09:13:53AM +0100, Thomas Petazzoni wrote:
> The Marvell Armada 375 and Armada 38x SOCs, which use the Cortex-A9
> CPU core, the PL310 cache and the Marvell PCIe hardware block are
> affected a L2/PCIe deadlock caused by a system erratum when hardware
> I/O coherency is used.
>
> This deadlock can be avoided by mapping the PCIe memory areas as
> strongly-ordered (note: MT_UNCACHED is strongly-ordered), and by
> removing the outer cache sync done in software. This is implemented in
> this patch by:
>
> * Registering a custom arch_ioremap_caller function that allows to
> make sure PCI memory regions are mapped MT_UNCACHED.
>
> * Adding at runtime the 'arm,io-coherent' property to the PL310 cache
> controller. This cannot be done permanently in the DT, because the
> hardware I/O coherency can only be enabled when CONFIG_SMP is
> enabled, in the current kernel situation.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
WARNING: multiple messages have this Message-ID (diff)
From: Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org>
To: Thomas Petazzoni
<thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Cc: Russell King <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>,
Will Deacon <Will.Deacon-5wv7dgnIgG8@public.gmane.org>,
"devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
Grant Likely
<grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org>,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>,
Albin Tonnerre <Albin.Tonnerre-5wv7dgnIgG8@public.gmane.org>,
"linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org"
<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
Jason Cooper <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org>,
Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>,
Sebastian Hesselbarth
<sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
Gregory Clement
<gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>,
Tawfik Bayouk <tawfik-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>,
Nadav Haklai <nadavh-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>,
Lior Amsalem <alior-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>,
Ezequiel Garcia
<ezequiel.garcia-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Subject: Re: [PATCHv5 3/4] ARM: mvebu: implement L2/PCIe deadlock workaround
Date: Mon, 19 May 2014 11:08:29 +0100 [thread overview]
Message-ID: <20140519100829.GE5113@arm.com> (raw)
In-Reply-To: <1400487234-4501-4-git-send-email-thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
On Mon, May 19, 2014 at 09:13:53AM +0100, Thomas Petazzoni wrote:
> The Marvell Armada 375 and Armada 38x SOCs, which use the Cortex-A9
> CPU core, the PL310 cache and the Marvell PCIe hardware block are
> affected a L2/PCIe deadlock caused by a system erratum when hardware
> I/O coherency is used.
>
> This deadlock can be avoided by mapping the PCIe memory areas as
> strongly-ordered (note: MT_UNCACHED is strongly-ordered), and by
> removing the outer cache sync done in software. This is implemented in
> this patch by:
>
> * Registering a custom arch_ioremap_caller function that allows to
> make sure PCI memory regions are mapped MT_UNCACHED.
>
> * Adding at runtime the 'arm,io-coherent' property to the PL310 cache
> controller. This cannot be done permanently in the DT, because the
> hardware I/O coherency can only be enabled when CONFIG_SMP is
> enabled, in the current kernel situation.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Acked-by: Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
next prev parent reply other threads:[~2014-05-19 10:08 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-19 8:13 [PATCHv5 0/4] ARM: implement workaround for Cortex-A9/PL310/PCIe deadlock Thomas Petazzoni
2014-05-19 8:13 ` Thomas Petazzoni
2014-05-19 8:13 ` [PATCHv5 1/4] ARM: mm: allow sub-architectures to override PCI I/O memory type Thomas Petazzoni
2014-05-19 8:13 ` Thomas Petazzoni
2014-05-19 8:13 ` [PATCHv5 2/4] ARM: mm: add support for HW coherent systems in PL310 Thomas Petazzoni
2014-05-19 8:13 ` Thomas Petazzoni
2014-05-19 9:37 ` Catalin Marinas
2014-05-19 9:37 ` Catalin Marinas
2014-05-19 8:13 ` [PATCHv5 3/4] ARM: mvebu: implement L2/PCIe deadlock workaround Thomas Petazzoni
2014-05-19 8:13 ` Thomas Petazzoni
2014-05-19 10:08 ` Catalin Marinas [this message]
2014-05-19 10:08 ` Catalin Marinas
2014-05-19 8:13 ` [PATCHv5 4/4] ARM: mvebu: use pci_ioremap_set_mem_type() to map PCI I/O as strongly ordered Thomas Petazzoni
2014-05-19 8:13 ` Thomas Petazzoni
2014-05-19 9:59 ` Catalin Marinas
2014-05-19 9:59 ` Catalin Marinas
2014-05-19 11:41 ` Thomas Petazzoni
2014-05-19 11:41 ` Thomas Petazzoni
2014-05-19 10:09 ` Catalin Marinas
2014-05-19 10:09 ` Catalin Marinas
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20140519100829.GE5113@arm.com \
--to=catalin.marinas@arm.com \
--cc=linux-arm-kernel@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.