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Date:   Wed, 21 May 2014 14:40:41 +0200
From:   Ralf Baechle <ralf@linux-mips.org>
To:     Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
Cc:     linux-mips@linux-mips.org, David Daney <ddaney.cavm@gmail.com>,
        James Hogan <james.hogan@imgtec.com>, kvm@vger.kernel.org,
        David Daney <david.daney@cavium.com>
Subject: Re: [PATCH 06/15] MIPS: Add minimal support for OCTEON3 to c-r4k.c
Message-ID: <20140521124041.GP10287@linux-mips.org>
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On Tue, May 20, 2014 at 04:47:07PM +0200, Andreas Herrmann wrote:

> +static inline void r4k_blast_dcache_page_dc128(unsigned long addr)
> +{
> +	R4600_HIT_CACHEOP_WAR_IMPL;

The R4600 has 32 byte cache lines that is this line will never be
executed on an R4600 thus can be dropped.

> +	blast_dcache128_page(addr);
> +}
> +
>  static void r4k_blast_dcache_page_setup(void)
>  {
>  	unsigned long  dc_lsize = cpu_dcache_line_size();
> @@ -121,6 +127,8 @@ static void r4k_blast_dcache_page_setup(void)
>  		r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
>  	else if (dc_lsize == 64)
>  		r4k_blast_dcache_page = r4k_blast_dcache_page_dc64;
> +	else if (dc_lsize == 128)
> +		r4k_blast_dcache_page = r4k_blast_dcache_page_dc128;


For another patch - let's see if this can be turned into a switch
construct which hopefully is more readable and produces just as
afficient code with reasonable vintage of gcc.

  Ralf