From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 6/7] drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating
Date: Tue, 27 May 2014 14:59:38 +0300 [thread overview]
Message-ID: <20140527115938.GL27580@intel.com> (raw)
In-Reply-To: <20140527114250.GI14357@phenom.ffwll.local>
On Tue, May 27, 2014 at 01:42:50PM +0200, Daniel Vetter wrote:
> On Mon, May 26, 2014 at 06:19:07PM +0300, Mika Kuoppala wrote:
> > deepak.s@linux.intel.com writes:
> >
> > > From: Deepak S <deepak.s@linux.intel.com>
> > >
> > > Signed-off-by: Deepak S <deepak.s@linux.intel.com>
> > > [vsyrjala: Fix merge fubmle where the code ended up in
> > > g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()]
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Acked-by: Ben Widawsky <ben@bwidawsk.net>
> > > ---
> > > drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
> > > 1 file changed, 11 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index 08dcdc5..0b73a6d 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -4026,7 +4026,18 @@ static void cherryview_enable_rps(struct drm_device *dev)
> > > GEN6_RP_UP_BUSY_AVG |
> > > GEN6_RP_DOWN_IDLE_AVG);
> > >
> > > + /* ToDo: Update the mem freq based on latest spec [CHV]*/
> >
> > Please do and consider fixing the vlv decoding. It seems to be off
> > too.
>
> Poke about this one here. Iirc the situation on vlv is simply terminal
> confusion, and iirc the current code matches reality of shipping vbiosen,
> but not any spec.
Yeah changed back here:
commit f6d519481b662d9fc52836e6e6107520f03e0122
Author: Deepak S <deepak.s@linux.intel.com>
Date: Thu Apr 3 21:01:28 2014 +0530
Revert "drm/i915/vlv: fixup DDR freq detection per Punit spec"
As per the inputs provided by hardware team we still use DDR
Rates as 0,1=800, 2=1066, 3=1333.
With this change, Turbo freqs used on current machines matches.
I think what we need is a comment there which states why
we're going against the spec, just to avoid future confusion
and someone accidentally changing it back again.
> I hope we're bettter for chv.
One can dream.
--
Ville Syrjälä
Intel OTC
next prev parent reply other threads:[~2014-05-27 12:00 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-23 15:30 [PATCH 0/7] Enable RC6/Turbo on CHV deepak.s
2014-05-23 15:30 ` [PATCH 1/7] drm/i915/chv: Enable Render Standby (RC6) for Cherryview deepak.s
2014-05-23 15:30 ` [PATCH 2/7] drm/i915/chv: Added CHV specific register read and write and Streamline CHV forcewake stuff deepak.s
2014-05-26 8:07 ` Daniel Vetter
2014-05-23 15:30 ` [PATCH 3/7] drm/i915/chv: Enable RPS (Turbo) for Cherryview deepak.s
2014-05-26 13:30 ` Mika Kuoppala
2014-05-26 13:54 ` Deepak S
2014-05-26 14:32 ` Ville Syrjälä
2014-05-27 3:29 ` Deepak S
2014-05-26 14:37 ` Mika Kuoppala
2014-05-27 3:29 ` Deepak S
2014-05-27 6:36 ` [PATCH v6] " deepak.s
2014-05-27 10:29 ` [PATCH v7] " deepak.s
2014-05-27 10:45 ` Mika Kuoppala
2014-05-27 11:44 ` Daniel Vetter
2014-05-23 15:30 ` [PATCH 4/7] drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0 deepak.s
2014-05-23 15:30 ` [PATCH 5/7] drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV deepak.s
2014-05-23 15:30 ` [PATCH 6/7] drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating deepak.s
2014-05-26 15:19 ` Mika Kuoppala
2014-05-27 11:42 ` Daniel Vetter
2014-05-27 11:59 ` Ville Syrjälä [this message]
2014-05-27 12:11 ` Deepak S
2014-05-27 12:13 ` Deepak S
2014-05-23 15:30 ` [PATCH 7/7] drm/i915/chv: Freq(opcode) request for CHV deepak.s
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