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diff for duplicates of <20140528015441.7816.62452@quantum>

diff --git a/a/content_digest b/N1/content_digest
index 9cfa8ab..e42f6dc 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -12,7 +12,8 @@
  "Subject\0Re: [PATCH 03/17] phy: ti-pipe3: add external clock support for PCIe PHY\0"
  "Date\0Tue, 27 May 2014 18:54:41 -0700\0"
  "To\0Nishanth Menon <nm@ti.com>"
- " Kishon Vijay Abraham I <kishon@ti.com>\0"
+  Kishon Vijay Abraham I <kishon@ti.com>
+ " Tero Kristo <t-kristo@ti.com>\0"
  "Cc\0Roger Quadros <rogerq@ti.com>"
   dt list <devicetree@vger.kernel.org>
   Paul Walmsley <paul@pwsan.com>
@@ -160,4 +161,4 @@
  "> Regards,\n"
  > Nishanth Menon
 
-00de0b4d37a1b76c68d022f07ceb53036b001f93f0e9aac4202880c78a210247
+10a683f799ec977b473d8fe9bc3d153e033ea83d18723aad2bfd5ad0a759ddfb

diff --git a/a/1.txt b/N2/1.txt
index f523ba5..77f299f 100644
--- a/a/1.txt
+++ b/N2/1.txt
@@ -80,7 +80,7 @@ Quoting Nishanth Menon (2014-05-15 05:33:13)
 > > 
 > > The apll clock node is like this
 > > 
-> > apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
+> > apll_pcie_in_clk_mux: apll_pcie_in_clk_mux at 4ae06118 {
 > >         compatible = "mux-clock";
 > >         clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
 > >         #clock-cells = <0>;
diff --git a/a/content_digest b/N2/content_digest
index 9cfa8ab..955d7f0 100644
--- a/a/content_digest
+++ b/N2/content_digest
@@ -8,23 +8,10 @@
  "ref\0CAGo_u6r8XtGHOvsfJKQMZ2ghFRz8x8_UhzyKE9jnwO6mJ2HYpQ@mail.gmail.com\0"
  "ref\05374B09F.2080803@ti.com\0"
  "ref\05374B409.3000607@ti.com\0"
- "From\0Mike Turquette <mturquette@linaro.org>\0"
- "Subject\0Re: [PATCH 03/17] phy: ti-pipe3: add external clock support for PCIe PHY\0"
+ "From\0mturquette@linaro.org (Mike Turquette)\0"
+ "Subject\0[PATCH 03/17] phy: ti-pipe3: add external clock support for PCIe PHY\0"
  "Date\0Tue, 27 May 2014 18:54:41 -0700\0"
- "To\0Nishanth Menon <nm@ti.com>"
- " Kishon Vijay Abraham I <kishon@ti.com>\0"
- "Cc\0Roger Quadros <rogerq@ti.com>"
-  dt list <devicetree@vger.kernel.org>
-  Paul Walmsley <paul@pwsan.com>
-  Krishnamoorthy
-  Balaji T <balajitk@ti.com>
-  linux-doc@vger.kernel.org <linux-doc@vger.kernel.org>
-  linux-pci@vger.kernel.org
-  Rajendra Nayak <rnayak@ti.com>
-  lkml <linux-kernel@vger.kernel.org>
-  Tero Kristo <t-kristo@ti.com>
-  linux-omap <linux-omap@vger.kernel.org>
- " linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>\0"
+ "To\0linux-arm-kernel@lists.infradead.org\0"
  "\00:1\0"
  "b\0"
  "Quoting Nishanth Menon (2014-05-15 05:33:13)\n"
@@ -109,7 +96,7 @@
  "> > \n"
  "> > The apll clock node is like this\n"
  "> > \n"
- "> > apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {\n"
+ "> > apll_pcie_in_clk_mux: apll_pcie_in_clk_mux at 4ae06118 {\n"
  "> >         compatible = \"mux-clock\";\n"
  "> >         clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;\n"
  "> >         #clock-cells = <0>;\n"
@@ -160,4 +147,4 @@
  "> Regards,\n"
  > Nishanth Menon
 
-00de0b4d37a1b76c68d022f07ceb53036b001f93f0e9aac4202880c78a210247
+1841003298c88eacead329def4546717653fd79764ad504919f4ebbf617575fc

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