From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: Re: [PATCH] drm/i915: make CRTC enable/disable asynchronous v3 Date: Fri, 30 May 2014 15:10:03 -0700 Message-ID: <20140530151003.631d073b@jbarnes-desktop> References: <1401473122-3451-1-git-send-email-jbarnes@virtuousgeek.org> <1401485332-2236-1-git-send-email-jbarnes@virtuousgeek.org> <20140530220218.GF10916@nuc-i3427.alporthouse.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-pd0-f172.google.com (mail-pd0-f172.google.com [209.85.192.172]) by gabe.freedesktop.org (Postfix) with ESMTP id BAB7C6EB54 for ; Fri, 30 May 2014 15:09:44 -0700 (PDT) Received: by mail-pd0-f172.google.com with SMTP id fp1so1384324pdb.17 for ; Fri, 30 May 2014 15:09:44 -0700 (PDT) In-Reply-To: <20140530220218.GF10916@nuc-i3427.alporthouse.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Chris Wilson Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, 30 May 2014 23:02:18 +0100 Chris Wilson wrote: > On Fri, May 30, 2014 at 02:28:52PM -0700, Jesse Barnes wrote: > > @@ -10326,7 +10466,7 @@ static int __intel_set_mode(struct drm_crtc *crtc, > > > > for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { > > if (intel_crtc->base.enabled) > > - dev_priv->display.crtc_disable(&intel_crtc->base); > > + intel_queue_crtc_disable(&intel_crtc->base); > > } > > This one looks odd. prepare_pipes are the pipes we have to turn off in > order to perform the modeset - which needs to be synchronous. > > intel_sync_crtcs(prepare_pipes) ? Well, they'll happen in order. But I was just looking at this code and in cases where ->mode_set messes with regs rather than staging it for ->crtc_enable we'll lose stuff here. Until we have that, doing the disables for the prepare_pipe synchronously is probably the right thing to do. -- Jesse Barnes, Intel Open Source Technology Center